發(fā)布時(shí)間：2018-07-15 07:39

【摘要】：汽車電子是現(xiàn)代汽車中一個(gè)發(fā)展迅猛的領(lǐng)域，，ECU（Electrical Control Unit）在其中扮演著非常重要的角色。為了實(shí)現(xiàn)汽車電子的智能化和網(wǎng)絡(luò)化，汽車中需要集成更多的ECU。但是ECU的核心部件微控制器卻被國(guó)外廠商長(zhǎng)期壟斷，這對(duì)大力發(fā)展國(guó)內(nèi)的汽車工業(yè)來說是一個(gè)障礙。所以進(jìn)行自主知識(shí)產(chǎn)權(quán)車用微控制器的設(shè)計(jì)和研發(fā)具有重要意義。 在分析了車用微控制器特點(diǎn)的基礎(chǔ)上，我們確定了研究目標(biāo)：實(shí)現(xiàn)一款兼容飛思卡爾CPU12指令集的16位車用微控制器。整個(gè)微控制器核心采用了單時(shí)鐘同步設(shè)計(jì)和微程序控制的總體設(shè)計(jì)方案，提高了系統(tǒng)的穩(wěn)定性和靈活性。本文主要負(fù)責(zé)微控制器運(yùn)算和譯碼部件的設(shè)計(jì)與驗(yàn)證。首先，本文提出了具有統(tǒng)一數(shù)據(jù)通路和快速運(yùn)算模塊的運(yùn)算部件。提出的數(shù)據(jù)通路使用一個(gè)運(yùn)算模塊就可以滿足一類指令的8位和16位有符號(hào)和無符號(hào)運(yùn)算，避免了運(yùn)算模塊的重復(fù)，從而減少了部件面積。性能評(píng)估的結(jié)果表明設(shè)計(jì)的運(yùn)算部件完全可以滿足微控制器的要求。其次，在對(duì)所有指令結(jié)構(gòu)和特征深入分析的基礎(chǔ)上，提出了一種兼容CPU12指令集的譯碼方案，結(jié)合提出的高效預(yù)取機(jī)制，可以快速讀入指令字節(jié)，從而加快了譯碼信息的產(chǎn)生，提高了微控制器的效率。 面對(duì)復(fù)雜設(shè)計(jì)帶來的驗(yàn)證挑戰(zhàn)，本文對(duì)驗(yàn)證語言和驗(yàn)證方法學(xué)進(jìn)行了相關(guān)研究，并搭建了基于UVM（Universal Verification Methodology）的可重用驗(yàn)證平臺(tái)，進(jìn)行了基于覆蓋率和斷言的模塊級(jí)驗(yàn)證，提高了設(shè)計(jì)和驗(yàn)證的質(zhì)量。本文設(shè)計(jì)了基于隨機(jī)約束的事務(wù)級(jí)指令發(fā)生器，此發(fā)生器可有效地產(chǎn)生各種符合指令集格式的指令，大大減少了人工定向激勵(lì)的編寫。結(jié)合針對(duì)接口信號(hào)和內(nèi)部狀態(tài)設(shè)計(jì)的并行斷言，加快了模塊級(jí)的調(diào)試過程和驗(yàn)證收斂，實(shí)現(xiàn)了部件的較全面驗(yàn)證。最后進(jìn)行了系統(tǒng)級(jí)的調(diào)試和FPGA原型測(cè)試。
[Abstract]:Electrical Control Unit (ECU) plays a very important role in modern automobile. In order to realize the intelligence and network of automobile electronics, more ECUs need to be integrated in automobile. However, the core component of ECU microcontroller has been monopolized by foreign manufacturers for a long time, which is an obstacle to the development of domestic automobile industry. Therefore, it is of great significance to design and develop independent intellectual property vehicle microcontrollers. On the basis of analyzing the characteristics of vehicle microcontroller, we have determined the research goal: to realize a 16-bit vehicle microcontroller compatible with Freescale CPU12 instruction set. The whole microcontroller core adopts the single clock synchronization design and the overall design scheme of microprogram control, which improves the stability and flexibility of the system. This paper is mainly responsible for the design and verification of microcontroller operation and decoding parts. First of all, this paper proposes a unified data path and fast operation module. Using one operation module, the proposed data path can satisfy the 8-bit and 16-bit signed and unsigned operations of a class of instructions, thus avoiding the repetition of the operation modules and thus reducing the area of the parts. The performance evaluation results show that the designed computing unit can fully meet the requirements of the microcontroller. Secondly, a decoding scheme compatible with CPU12 instruction set is proposed on the basis of in-depth analysis of all instruction structures and features. Combined with the proposed efficient prefetching mechanism, it can quickly read instruction bytes, thus speeding up the generation of decoding information. The efficiency of microcontroller is improved. In the face of the verification challenges brought by complex design, this paper studies the verification language and verification methodology, builds a reusable verification platform based on UVM (Universal Verification Methodology), and implements modular verification based on coverage and assertion. The quality of design and verification is improved. In this paper, a transaction level instruction generator based on random constraints is designed. This generator can effectively generate instructions in accordance with instruction set format and greatly reduce the writing of manual directional excitation. Combined with the parallel assertions designed for interface signals and internal states, the debugging process and verification convergence at the module level are accelerated, and the complete verification of the components is realized. Finally, system level debugging and FPGA prototype test are carried out.
【學(xué)位授予單位】：湖南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP332

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