本文關(guān)鍵詞：新型硅通孔（TSV）的電磁特性研究，由筆耕文化傳播整理發(fā)布。

參考文獻(xiàn)

[1]魏禎.三維高密度集成電路中錐形硅通孔電特性研究.上海交通大學(xué)碩士學(xué)位論文.2013.12

[2]Qijun Lu, Zhangming Zhu, Member, IEEE, Yintang Yang, and Ruixue Ding. Electrical Modeling and Characterization of Shield Differential Through-Silicon Vias

[3] John H. Lau. Evolution, challenge, and outlook of TSV, 3D IC integration and 3d silicon integration

[4] John H. Lau. Overview and outlook of through-silicon via (TSV) and 3D integrations

[5] Joohee Kim, Jun So Pak, Jonghyun Cho, Eakhwan Song, Jeonghyeon Cho, Heegon Kim, Taigon Song, Junho Lee, Hyungdong Lee, Kunwoo Park, Seungtaek Yang, Min-Suk Suh, Kwang-Yoo Byun, and Joungho Kim. High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)

[6]劉培生，黃金鑫，仝良玉，，沈海軍，施建根.硅通孔技術(shù)的發(fā)展與挑戰(zhàn)

[7]李文石，馬強(qiáng)，李波.三維集成技術(shù)的發(fā)展研究

[8]王鳳娟.基于硅通孔(TSV)的三維集成電路(3D IC)關(guān)鍵特性分析.西安電子科技大學(xué)博士學(xué)位論文.2014.3

[9] MOTOYOSHI M. Through-silicon via (TSV) [J]. Proc IEEE, 2009, 97(1): 43-48.

[10] CHUA T T, HO S W, LI H Y, et al. 3D interconnection process development and integration with low stress TSV [C]// 60th Electronic Components and Technology Conference. Las Vegas, USA: IEEE, 2010. [11] CHUNG K W, SHI H S, LU S T, et al. 3D stacking DRAM using TSV technology and microbump interconnect [C]//

International Microsystems Packaging Assembly and Circuits Technology

Conference. Taipei, Taiwan: IEEE, 2010.

[12] XU G W, YAN P L, XIAO C, et al. Wafer-level chip-to-wafer(C2W) integration of high-sensitivity MEMS and ICs [C]// 12th International Conference on Electronic Packaging Technology & High Density Packaging. Shanghai, China: [s.n.], 2011.

[13] SAKUMA K, ANDRY P S, TSANG C K, et al. 3D chip-stacking technology with

through-silicon via and low-volume lead free interconnections [J]. IBM J Res Dev, 2008, 52(6): 611-622.

[14] CHENG T Y, WANG C D, CHIOU Y P, et al. A new macro-n model for through-silicon vias on 3-D IC using conformal mapping method [J]. IEEE Microwave Wireless Compon Lett, 2012, 22(6): 303-305.

[15] QIAN L B, ZHU Z M, YANG Y T. Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits [J]. Microelectron J, 2012, 43(2): 128-133.

[16] YOON K, KIM G, LEE W, et al. Modeling and analysis of coupling between TSVs, metal, and RDL interconnects in TSV-based 3D IC with silicon interposer [C]// 11th Electronics Packaging Technology Conference. Singapore: IEEE, 2009.

[17] CASSID Y C, KRAFT J, CARNIELLO S, et al. Through silicon via reliability [J]. Trans Device Mater Res, 2012, 12(2): 285-295.

[18] LADANI L J. Numerical analysis of thermo-mechanical reliability of through silicon vias (TSVs) and solder interconnects in 3-dimensional integrated circuits [J].

Microelectron Eng, 2010, 87(2): 208-215.

[19] SUNG K J, CHOI K S, LIM B K. Solder bump maker with coining process on TSV chips for 3D packages [C]// 11th International Conference on Electronic Packaging Technology and High Density Packaging. Xi'an, China: [s.n.], 2010.

[20] PARES G, BRESSON N, MOREAU S, et al. Effects of stress in polysilicon via-first TSV technology [C]//12th Electronics Packaging Technology Conference. Singapore: IEEE, 2010.

[21] POLYAKOW A, GROB T, HOVENKAMO R A, et al. Comparison of via-fabrication

through-wafer electrical interconnect applications [C]//54th Electronic Components and Technology Conference. Las Vegas, Nevada, USA: IEEE, 2004.

[22] VILLANUEVA G, PLAZA J A, SANCHEZáNCHEZ A, et al. Drie based novel technique for AFM probes fabrication [J]. Microelectron Eng, 2007, 84(5/6/7/8): 1132-1135.

[23] HOLLY R, HINGER L. Fabrication of silicon vertical taper structures using KOH anisotropic etching [J]. Microelectron Eng, 2006, 83(4/5/6/7/8/9): 1430 -1433.

[24] RANGANATHAN N, LEE D Y, YOUHE L, et al. Influence of bosch etch process on electrical isolation of TSV structures [J]. IEEE Trans Compon Pack Man, 2011, 1(10): 1497-1507.

[25] TANG C W, YOUNG H T, LI K M. Innovative through-silicon-via formation approach for wafer-level packaging applications [J]. J Micromech Microeng, 2012, 22(4): 045019.

[26] RANGANATHAN N, PRASAD K, BALASUBRAMANIAN N, et al. A study of

thermo-mechanical stress and its impact on through-silicon vias [J]. J Micromech Microeng, 2008, 18(7): 075018.

[27] HONG S J, JUN J H, JUNG J P, et al. Sn bumping without photoresist mould and Si dice stacking for 3-D packaging [J]. IEEE Trans Adv Packg, 2010, 33(4): 912-917.

[28] KUO C W, TSAI H Y. Thermal stress analysis and failure mechanisms for through silicon via array [C]// 6th International Conference on Microsystems, Packaging, Assembly and Circuits Technology Conference. Taipei, China: IEEE, 2011.

[29] GAGNARD X, MOURIER T. Through silicon via: from the CMOS imager sensor wafer level package to the 3D integration [C] //18th European Workshop on

Materials for Advanced Metallization. Grenoble, France: [s.n.], 2009.

[30] LAI M F, LI S W, SHIH J Y, et al. Wafer-level three-dimensional integrated circuits (3D IC): schemes and key technologies [J]. Microelectron Eng, 2011, 88(11):

3282-3286.

[31] WANG Q D, GUO X P, WANG H J, et al. Characteristics of high frequency and high density through silicon vias (TSVs)[C] //11th International Conference on Electronic Packaging Technology & High Density Packaging. Xi'an, China: [s.n.], 2010.

[32] KOYANAGI M, FUKUSHIMA T, TANAKA T. High-density through silicon vias for 3-D LSIs [J]. Proc IEEE Int Conf IC Des Technol, 2009, 97(1): 49-59.

[33] JOSEPH A J, GILLIS J D, DOHERTY M, et al. Through-silicon vias enable

next-generation SiGe power amplifiers for wireless communications [J]. IBM J Res Dev, 2008, 52(6): 635-648.

[34] PARèS G, BRESSON N, MINORET S, et al. Through silicon via technology using tungsten metallization [C] // IEEE International Conference on IC Design &

Technology. China: IEEE, 2011.

[34] 盧啟軍.新型硅通孔（TSV）的電磁特性研究.西安電子科技大學(xué)博士學(xué)位論文

[35] (2013). International Technology Roadmap for Semiconductors. [Online]. Available:

[36] Z. Xu and J.-Q. Lu, “High-speed design and broadband modeling of

through-strata-vias (TSVs) in 3D integration,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 1, no. 2, pp. 154–162, Feb. 2011.

*37+ C. Xu, H. Li, R. Suaya, and K. Banerjee, “Compact AC modeling and performance

博泰典藏網(wǎng)btdcw.com包含總結(jié)匯報(bào)、表格模板、自然科學(xué)、醫(yī)藥衛(wèi)生、高中教育、經(jīng)管營(yíng)銷(xiāo)、工程科技、外語(yǔ)學(xué)習(xí)、行業(yè)論文以及三維高密度集成電路中錐形硅通孔電特性等內(nèi)容。

本文共2頁(yè)12

  本文關(guān)鍵詞：新型硅通孔（TSV）的電磁特性研究，由筆耕文化傳播整理發(fā)布。