發(fā)布時間：2018-06-10 01:35

  本文選題：三維可重構陣列 + 自主容錯��； 參考：《南京航空航天大學》2013年碩士論文

【摘要】：隨著集成電路技術的飛速發(fā)展，數(shù)字電子系統(tǒng)的集成度大幅提高，在生命周期內(nèi)發(fā)生故障的概率也隨之增加�？芍貥嬘布�具有功能靈活、開發(fā)周期短等優(yōu)點，，已廣泛應用于航空航天等領域的關鍵電子系統(tǒng)中，由于工作環(huán)境惡劣且人工難以維護，對可重構硬件的可靠性要求更高。因此，以提高可靠性為目標的可重構硬件容錯設計具有重要意義。 可重構硬件的自主容錯是指在不需要外部控制器進行控制的情況下，實現(xiàn)故障自主修復。目前二維可重構硬件的自主容錯方法中，重布線機制不易實現(xiàn)，特別是在一些大規(guī)模系統(tǒng)中，布線擁塞和延遲現(xiàn)象嚴重，導致容錯時間開銷大，容錯能力不高。三維陣列結構可顯著減少布線長度，提高布線過程布通率和布線機制靈活性，給可重構硬件的容錯方法設計提供了新思路。 本文利用三維陣列結構在布線靈活性方面的優(yōu)勢，對三維可重構陣列的自主容錯方法進行研究，論文的主要研究工作如下： （1）設計了一種三維結構的可重構陣列，可有效改善二維可重構硬件重布線機制不靈活，容錯控制復雜度隨陣列規(guī)模增大而增加，難以大規(guī)模實現(xiàn)等問題，并且在此結構上對功能細胞和三維開關塊進行了容錯設計，使可重構陣列具有自主容錯能力。三維開關塊用于實現(xiàn)功能細胞在六個方向上的信息傳遞，提高了布線機制靈活性的同時，還具有在線自測試與自修復能力；功能細胞內(nèi)部設有容錯控制模塊，可實現(xiàn)細胞的在線自主容錯，減少容錯控制復雜度。 （2）對可重構硬件的自主容錯方法進行了研究，采用在線分布式輸入測試向量的方法，能夠?qū)�故障進行精確定位，測試速度快且測試機制實現(xiàn)簡單；容錯過程中，采用分層修復方法，根據(jù)診斷結果執(zhí)行相應修復機制，對細胞內(nèi)底層冗余資源和可重構陣列空閑互連資源進行合理利用，充分提高資源利用率和容錯速率。 （3）本文最后以四位并行乘法器和四位加法/減法器為例，在三維可重構陣列上實現(xiàn)功能映射，對其進行仿真和下板測試，驗證了可重構陣列的邏輯功能與自主容錯能力，并且在容錯能力、硬件資源開銷和容錯時間開銷三方面與其他典型可重構硬件容錯技術進行了分析對比，說明本文提出的三維可重構陣列自主容錯方法具有容錯能力高，硬件資源開銷小和容錯速度快等優(yōu)勢。
[Abstract]:With the rapid development of integrated circuit technology, the integration of digital electronic system has been greatly improved, and the probability of failure in the life cycle has also increased. Reconfigurable hardware has the advantages of flexible function and short development cycle. It has been widely used in the key electronic systems in aerospace and other fields. Because of the harsh working environment and difficult to maintain, the reliability of reconfigurable hardware is higher than that of reconfigurable hardware. Therefore, it is of great significance to improve the reliability of reconfigurable hardware fault-tolerant design. The autonomous fault tolerance of reconfigurable hardware refers to the implementation of autonomous fault recovery without the need of external controller control. At present, the rerouting mechanism is not easy to implement in two-dimensional reconfigurable hardware, especially in some large-scale systems, the routing congestion and delay are serious, resulting in a large amount of fault-tolerant time overhead and low fault-tolerant ability. Three-dimensional array structure can significantly reduce routing length, improve routing process routing rate and routing mechanism flexibility, and provide a new idea for fault tolerant design of reconfigurable hardware. This paper makes use of the advantages of three-dimensional array structure in routing flexibility. The main work of this paper is as follows: 1) A reconfigurable array with 3D structure is designed, which can effectively improve the rerouting mechanism of two-dimensional reconfigurable hardware. The complexity of fault-tolerant control increases with the increase of array size, which is difficult to implement on a large scale. In this structure, fault-tolerant design for functional cells and 3D switching blocks is carried out to make the reconfigurable array have autonomous fault-tolerant capability. Three-dimensional switch block is used to realize information transmission in six directions of functional cells, which improves the flexibility of routing mechanism, and also has the ability of on-line self-testing and self-repairing, and has fault-tolerant control module inside functional cells. It can realize the on-line autonomous fault-tolerant of cells and reduce the complexity of fault-tolerant control. (X2) the autonomous fault-tolerant method of reconfigurable hardware is studied. The method of on-line distributed input test vector can accurately locate the fault. In the process of fault tolerance, the hierarchical repair method is used to carry out the corresponding repair mechanism according to the diagnosis results, and the redundant resources in the bottom layer of the cell and the idle interconnection resources of the reconfigurable array are reasonably utilized. Finally, taking four bit parallel multiplier and four bit addition / subtraction as examples, we implement functional mapping on 3D reconfigurable array, simulate it and test it on the bottom board. The logic function and autonomous fault-tolerant ability of reconfigurable array are verified and compared with other typical reconfigurable hardware fault-tolerant techniques in three aspects: fault-tolerant capability, hardware resource overhead and fault-tolerant time cost. It is shown that the autonomous fault-tolerant method of 3D reconfigurable array presented in this paper has the advantages of high fault-tolerant capability, low cost of hardware resources and fast fault-tolerant speed.
【學位授予單位】：南京航空航天大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP302.8

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本文編號：2001523