發(fā)布時(shí)間：2018-06-10 07:07

  本文選題：低功耗 + 高速緩存　； 參考：《湖南大學(xué)》2013年碩士論文

【摘要】：電子工藝技術(shù)的迅猛發(fā)展大大提高了處理器的集成度和工作速度，雖然性能得到大幅度的提升，但處理器功耗也迅速增加。功耗增加不僅導(dǎo)致芯片升溫，降低芯片的穩(wěn)定性，而且也增加了芯片的設(shè)計(jì)難度和縮短了芯片壽命。Cache作為處理器重要的組成部分，由于其需要具備容量大、速度快、訪問頻繁等特性，使之成為處理器芯片功耗的主要來源，因此設(shè)計(jì)低功耗Cache結(jié)構(gòu)能有效地降低處理器整體功耗，對(duì)嵌入式系統(tǒng)的性能提高有重大意義。本文針對(duì)嵌入式系統(tǒng)環(huán)境，提出了兩種改進(jìn)的可重構(gòu)Cache低功耗算法。本文的主要工作成果如下： (1)綜合考慮容量與相聯(lián)度對(duì)Cache性能影響的基礎(chǔ)上，提出了一種降維可重構(gòu)Cache算法。該算法根據(jù)Cache結(jié)構(gòu)參數(shù)對(duì)不同應(yīng)用程序影響的權(quán)值大小不同，先確定容量最優(yōu)解，再確定相聯(lián)度最優(yōu)解的檢索順序來進(jìn)行Cache參數(shù)配置；其次，算法將對(duì)檢索效果進(jìn)行判斷，若檢索效果不佳，則繼續(xù)采用先確定相聯(lián)度最優(yōu)解后確定容量最優(yōu)解的檢索順序，若程序仍處于不穩(wěn)定狀態(tài)，則動(dòng)態(tài)調(diào)整閥值，朝失效率減少的方向搜索最優(yōu)Cache結(jié)構(gòu)。仿真實(shí)驗(yàn)結(jié)果表明，該算法能有效地降低Cache失效率和減少Cache能耗損失。 (2)在降維可重構(gòu)Cache算法的基礎(chǔ)上，提出了一種基于指令工作集的可重構(gòu)Cache算法。該算法通過記錄高頻出現(xiàn)的程序段指令工作集簽名及其最佳Cache配置參數(shù)，，若程序發(fā)生變化時(shí)，通過分析比較程序段指令工作集簽名，采用特征值匹配的方法預(yù)重構(gòu)Cache，若程序仍然處于不穩(wěn)定狀態(tài)，則從當(dāng)前狀態(tài)以降維重構(gòu)的方法繼續(xù)調(diào)整Cache容量和相聯(lián)度。仿真實(shí)驗(yàn)結(jié)果表明，相比降維算法，該算法能夠有效提高監(jiān)測(cè)程序變化的準(zhǔn)確度和優(yōu)化重構(gòu)路徑，并且能有效提高Cache性能。 本文基于Sim-panalyzer平臺(tái)對(duì)算法進(jìn)行了仿真模擬，實(shí)驗(yàn)結(jié)果與理論推導(dǎo)相符合。與近年來相關(guān)論文的比較驗(yàn)證了本設(shè)計(jì)的創(chuàng)新性和實(shí)用性。本文的低功耗重構(gòu)算法為生產(chǎn)嵌入式低功耗產(chǎn)品提供了技術(shù)支持。
[Abstract]:The rapid development of electronic technology has greatly improved the integration and working speed of the processor. Although the performance has been greatly improved, the power consumption of the processor has also increased rapidly. The increase of power consumption not only causes the chip to warm up and reduce the stability of the chip, but also increases the design difficulty of the chip and shortens the life of the chip. Cache is an important part of the processor. Access frequency and other characteristics make it the main source of power consumption in processor chips. Therefore, the design of low power cache architecture can effectively reduce the overall power consumption of the processor, and it is of great significance to improve the performance of embedded systems. In this paper, two improved reconfigurable cache low power algorithms are proposed for embedded system environment. The main results of this paper are as follows: 1) based on the effect of capacity and coherence on cache performance, a dimensionally reduced reconfigurable cache algorithm is proposed. According to the influence of cache structure parameters on the weights of different applications, the algorithm first determines the optimal solution of capacity, then determines the retrieval order of the optimal solution of association degree to configure the Cache parameters; secondly, the algorithm will judge the retrieval effect. If the retrieval effect is not good, the search order of the optimal solution of the degree of association and the optimal solution of the capacity is determined first. If the program is still in an unstable state, the threshold is dynamically adjusted to search for the optimal cache structure in the direction of reducing the failure rate. Simulation results show that the proposed algorithm can effectively reduce the cache failure rate and reduce the energy loss of cache. On the basis of dimensionality reduction reconfigurable cache algorithm, a reconfigurable cache algorithm based on instruction working set is proposed. The algorithm records the high frequency program segment instruction working set signature and its optimal cache configuration parameter, and analyzes and compares the program segment instruction working set signature if the program changes. The method of eigenvalue matching is used to pre-reconstruct Cache.If the program is still in an unstable state, the cache capacity and the degree of association can be adjusted continuously from the current state by dimensionality reduction. The simulation results show that the algorithm can effectively improve the accuracy of monitoring program change, optimize the reconstruction path, and improve the performance of cache, compared with the dimensionality reduction algorithm. This paper simulates the algorithm based on Sim-p analyzer platform. The experimental results are in agreement with the theoretical derivation. The comparison with related papers in recent years verifies the innovation and practicability of this design. The low-power reconstruction algorithm in this paper provides technical support for the production of embedded low-power products.
【學(xué)位授予單位】：湖南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332

【參考文獻(xiàn)】

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本文編號(hào)：2002388