異構五核XDSP調度機制的設計與實現(xiàn)
發(fā)布時間：2018-07-15 13:52
【摘要】：高速發(fā)展的處理器技術已經(jīng)發(fā)生了革命性的變化，多核處理器逐漸代替單核處理器成為處理器技術主流。作為通用微處理器的一個分支，數(shù)字信號處理器即DSP也跨進了以多核，尤其是異構多核DSP為主導的高速發(fā)展時代。 嵌入式異構多核DSP處理器是軟硬件協(xié)同設計的面向應用的專用微處理器。從應用角度而言，提升用戶體驗的努力不僅僅體現(xiàn)在升級操作系統(tǒng)，，更在于開發(fā)更合適的硬件機制。任務調度是操作系統(tǒng)和硬件系統(tǒng)需要共同關注的環(huán)節(jié)。異構多核處理器體系結構的出現(xiàn)為任務調度問題帶來了新的變化，如何設計能夠有效實現(xiàn)任務調度的硬件機制來支撐任務調度算法實現(xiàn)，使異構多核處理器系統(tǒng)能夠充分發(fā)揮性能已經(jīng)成為亟待解決的問題。在嵌入式異構多核DSP處理器操作系統(tǒng)中，多核任務的調度根據(jù)多核任務調度算法實現(xiàn)。而多核任務調度的算法運作實際上是通過調用調度機制的驅動程序，從而驅動底層硬件運作的過程。在整個任務調度機制中，底層的硬件是基礎，驅動程序是支撐。 本文以國防科技大學計算機學院研制的高性能異構五核XDSP設計工程為背景，為XDSP設計了能夠有效支持多核任務調度的底層硬件機制和配套的驅動程序，是XDSP多核系統(tǒng)能夠順利運行并發(fā)揮其性能的保障。本文主要完成了以下工作： 基于XDSP的體系結構特點和豐富的片上資源，為XDSP設計了硬件調度機制，實現(xiàn)了MCU子系統(tǒng)和DSP子系統(tǒng)間的數(shù)據(jù)通信和MCU對DSP子系統(tǒng)的控制； 配合XDSP多核調度的硬件機制，設計了配套的驅動程序，包括多種BOOT模式下的BOOT程序，實施調度和任務同步的交叉中斷處理程序等，為調度機制的運行提供了驅動支撐； 分別在模塊級和系統(tǒng)級對調度機制進行了模擬功能驗證，驗證中組合使用了覆蓋率驅動的驗證方法，基于斷言的驗證方法和軟硬件協(xié)同仿真等驗證方法； 實現(xiàn)了XDSP的FPGA原型設計，對調度機制進行了較全面的系統(tǒng)級仿真驗證，并據(jù)此實現(xiàn)了JPEG解碼程序在XDSP上的任務分派和調度。
[Abstract]:The rapid development of processor technology has undergone a revolutionary change, multi-core processors have gradually replaced single-core processors into the mainstream of processor technology. As a branch of universal microprocessor, DSP (Digital signal processor) has also stepped into the era of high speed development with multi-core, especially heterogeneous multi-core DSP. Embedded heterogeneous multi-core DSP processor is an application-oriented microprocessor which is codesigned by hardware and software. From an application point of view, efforts to enhance the user experience are not only reflected in upgrading the operating system, but also in developing more appropriate hardware mechanisms. Task scheduling is a link that the operating system and hardware system need to pay attention to. The emergence of heterogeneous multi-core processor architecture has brought new changes to the task scheduling problem. How to design a hardware mechanism that can effectively implement task scheduling to support the implementation of task scheduling algorithm. It has become an urgent problem to make heterogeneous multi-core processor system give full play to its performance. In embedded heterogeneous multi-core DSP processor operating system, the scheduling of multi-core tasks is based on multi-core task scheduling algorithm. The algorithm operation of multi-core task scheduling is actually the process of driving the underlying hardware operation by calling the driver of the scheduling mechanism. In the whole task scheduling mechanism, the underlying hardware is the foundation and the driver is the support. Based on the design engineering of high performance heterogeneous five-core XDSP developed by computer School of National University of National Defense Science and Technology, this paper designs the underlying hardware mechanism and supporting driver for XDSP, which can effectively support multi-core task scheduling. It is the guarantee that XDSP multi-core system can run smoothly and give full play to its performance. The main work of this paper is as follows: based on the architecture characteristics of XDSP and abundant on-chip resources, the hardware scheduling mechanism is designed for XDSP, the data communication between MCU subsystem and DSP subsystem is realized and MCU controls DSP subsystem; With the hardware mechanism of XDSP multi-core scheduling, a complete set of drivers is designed, including the boot program in various boot modes, the cross-interrupt processing program for scheduling and task synchronization, and so on. It provides driving support for the operation of the scheduling mechanism, and simulates the scheduling mechanism at the module level and the system level, and combines the coverage driven verification method in the verification. The verification methods based on assertion and hardware / software co-simulation are implemented, the FPGA prototype design of XDSP is implemented, and the scheduling mechanism is verified by system-level simulation. Based on this, the task assignment and scheduling of JPEG decoding program on XDSP are realized.
【學位授予單位】：國防科學技術大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP332
本文編號：2124290
[Abstract]:The rapid development of processor technology has undergone a revolutionary change, multi-core processors have gradually replaced single-core processors into the mainstream of processor technology. As a branch of universal microprocessor, DSP (Digital signal processor) has also stepped into the era of high speed development with multi-core, especially heterogeneous multi-core DSP. Embedded heterogeneous multi-core DSP processor is an application-oriented microprocessor which is codesigned by hardware and software. From an application point of view, efforts to enhance the user experience are not only reflected in upgrading the operating system, but also in developing more appropriate hardware mechanisms. Task scheduling is a link that the operating system and hardware system need to pay attention to. The emergence of heterogeneous multi-core processor architecture has brought new changes to the task scheduling problem. How to design a hardware mechanism that can effectively implement task scheduling to support the implementation of task scheduling algorithm. It has become an urgent problem to make heterogeneous multi-core processor system give full play to its performance. In embedded heterogeneous multi-core DSP processor operating system, the scheduling of multi-core tasks is based on multi-core task scheduling algorithm. The algorithm operation of multi-core task scheduling is actually the process of driving the underlying hardware operation by calling the driver of the scheduling mechanism. In the whole task scheduling mechanism, the underlying hardware is the foundation and the driver is the support. Based on the design engineering of high performance heterogeneous five-core XDSP developed by computer School of National University of National Defense Science and Technology, this paper designs the underlying hardware mechanism and supporting driver for XDSP, which can effectively support multi-core task scheduling. It is the guarantee that XDSP multi-core system can run smoothly and give full play to its performance. The main work of this paper is as follows: based on the architecture characteristics of XDSP and abundant on-chip resources, the hardware scheduling mechanism is designed for XDSP, the data communication between MCU subsystem and DSP subsystem is realized and MCU controls DSP subsystem; With the hardware mechanism of XDSP multi-core scheduling, a complete set of drivers is designed, including the boot program in various boot modes, the cross-interrupt processing program for scheduling and task synchronization, and so on. It provides driving support for the operation of the scheduling mechanism, and simulates the scheduling mechanism at the module level and the system level, and combines the coverage driven verification method in the verification. The verification methods based on assertion and hardware / software co-simulation are implemented, the FPGA prototype design of XDSP is implemented, and the scheduling mechanism is verified by system-level simulation. Based on this, the task assignment and scheduling of JPEG decoding program on XDSP are realized.
【學位授予單位】：國防科學技術大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP332
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相關期刊論文 前2條
1 陳芳園;張冬松;王志英;;異構多核處理器體系結構設計研究[J];計算機工程與科學;2011年12期
2 劉必慰;陳書明;汪東;;先進微處理器體系結構及其發(fā)展趨勢[J];計算機應用研究;2007年03期
本文編號：2124290
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