一種任意時間片長度對CPU上下文切換代價影響消除的新方法
發(fā)布時間：2018-07-16 14:06
【摘要】：分析并量化了操作系統任務調度時上下文切換對CPU性能影響,得出了任務上下文切換代價對CPU效率影響關系.在此影響關系的基礎上,提出了一種可行的Hyper-Scheduling方法.此方法通過在CPU內部設置一條特殊的任務切換專用流水線數據通路,并在通用寄存器堆上寄生一個相同的寄存器堆(影子寄存器堆)和監(jiān)視訪存狀態(tài)的寄生邏輯,來監(jiān)視各硬件資源運行情況,實現在CPU硬件資源閑置狀態(tài)時進行預先數據準備或任務保存.當任務切換時將這條特殊數據通路與CPU主數據通路流水線進行交換,使上下文切換時間可趨近于零,任務切換代價被消除,上下文頻繁切換或時間片長度縮短至近于零的情況下,CPU效率仍能夠保持性能最大化.
[Abstract]:The influence of context switching on CPU performance is analyzed and quantified, and the relationship between task context switching cost and CPU efficiency is obtained. Based on the relationship, a feasible Hyper-Scheduling method is proposed. In this method, a special task switching special pipeline data path is set up inside the CPU, and a common register file (shadow register file) is parasitized on the general register file and the parasitic logic of monitoring the memory access state is monitored. To monitor the running situation of each hardware resource, the CPU hardware resource can be prepared or saved in advance when the CPU hardware resource is idle. When the task switches, the special data path is exchanged with the CPU main data path pipeline, so that the context switching time can approach zero, and the task switching cost is eliminated. The CPU efficiency can be maximized when the context is switched frequently or the time slice length is shortened to near zero.
【作者單位】： 華東師范大學可信物聯網產學研聯合研發(fā)中心;華東師范大學軟件學院;
【分類號】：TP332
本文編號：2126629
[Abstract]:The influence of context switching on CPU performance is analyzed and quantified, and the relationship between task context switching cost and CPU efficiency is obtained. Based on the relationship, a feasible Hyper-Scheduling method is proposed. In this method, a special task switching special pipeline data path is set up inside the CPU, and a common register file (shadow register file) is parasitized on the general register file and the parasitic logic of monitoring the memory access state is monitored. To monitor the running situation of each hardware resource, the CPU hardware resource can be prepared or saved in advance when the CPU hardware resource is idle. When the task switches, the special data path is exchanged with the CPU main data path pipeline, so that the context switching time can approach zero, and the task switching cost is eliminated. The CPU efficiency can be maximized when the context is switched frequently or the time slice length is shortened to near zero.
【作者單位】： 華東師范大學可信物聯網產學研聯合研發(fā)中心;華東師范大學軟件學院;
【分類號】：TP332
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