發(fā)布時(shí)間：2018-06-22 04:23

  本文選題：模數(shù)轉(zhuǎn)換器 + 逐次逼近ADC��； 參考：《電子科技大學(xué)》2016年博士論文

【摘要】：作為連接外部世界模擬信號(hào)和系統(tǒng)內(nèi)部數(shù)字信號(hào)的橋梁,模擬數(shù)字轉(zhuǎn)換器(ADC)廣泛應(yīng)用于數(shù)字多媒體、通信、生物醫(yī)療以及傳感控制等領(lǐng)域,其速度、精度以及功耗等性能指標(biāo)直接影響著整機(jī)系統(tǒng)的處理能力。隨著工藝尺寸的不斷縮小以及電源電壓的不斷降低,模擬電路設(shè)計(jì)面臨巨大挑戰(zhàn)。但逐次逼近模數(shù)轉(zhuǎn)換器(SAR ADC)僅含一個(gè)模擬模塊,其整體結(jié)構(gòu)簡(jiǎn)單且功耗面積小,因此在小尺寸工藝下易于實(shí)現(xiàn),較其他ADC結(jié)構(gòu)優(yōu)勢(shì)凸顯。然而,由于其串行的工作模式,SAR ADC的速度較低,造成其應(yīng)用受限。另一方面,隨著ADC分辨率增大,對(duì)DAC電容的匹配精度要求提高,導(dǎo)致電容值急劇增大。這使得SAR ADC在高精度應(yīng)用中受到功耗和速度的雙重限制。針對(duì)這些問題,本文進(jìn)行了深入的研究和討論,包括非二進(jìn)制編碼原理、適用于非二進(jìn)制量化的DAC結(jié)構(gòu)、非二進(jìn)制DAC的速度優(yōu)化設(shè)計(jì)方案、電容失配的校正技術(shù)、異步時(shí)序電路的設(shè)計(jì)以及自校正帶隙基準(zhǔn)電路的設(shè)計(jì)等,主要的研究工作和創(chuàng)新如下:1.采用非二進(jìn)制量化算法的SAR ADC系統(tǒng)架構(gòu)研究:本文首先對(duì)傳統(tǒng)的二進(jìn)制SAR ADC的轉(zhuǎn)換速度進(jìn)行了理論分析。由于量化每一位時(shí)DAC的建立精度都需要達(dá)到0.5 LSB,導(dǎo)致DAC所需的建立時(shí)間較長(zhǎng),限制了ADC整體的采樣速率。為此,本文對(duì)非二進(jìn)制量化算法進(jìn)行了研究。通過將數(shù)字編碼的基數(shù)設(shè)為小于2的分?jǐn)?shù),可以在量化過程中引入冗余量,使得同一個(gè)輸入信號(hào)可以被兩個(gè)不同的非二進(jìn)制編碼量化,從而放寬對(duì)DAC建立精度的要求。然后,針對(duì)分?jǐn)?shù)權(quán)重量化算法在實(shí)際設(shè)計(jì)中存在匹配差、編碼轉(zhuǎn)換時(shí)存在截?cái)嗾`差、無法利用分段電容陣列等問題,提出了基于整數(shù)權(quán)重的量化算法。在此基礎(chǔ)上,又提出了兩種適用于非二進(jìn)制量化的DAC結(jié)構(gòu),即基于共模電壓復(fù)位的DAC和電容分裂式DAC。通過將DAC產(chǎn)生的參考電壓置于冗余范圍的中間,將DAC的建立精度從0.5 LSB擴(kuò)大到冗余量的一半。最后,提出了一種對(duì)DAC電容進(jìn)行優(yōu)化設(shè)計(jì)的方案,以最大限度地利用冗余量的優(yōu)勢(shì)來提高整體的轉(zhuǎn)換速度。2.SAR ADC電容失配的校正技術(shù)研究:為了利用小電容實(shí)現(xiàn)高精度的SAR ADC,需要對(duì)電容失配進(jìn)行校正。本文提出了三種不同的校正技術(shù),包括模擬域前臺(tái)校正、模擬域后臺(tái)校正以及數(shù)字域后臺(tái)校正。其中兩種模擬域校正適用于二進(jìn)制SAR ADC,其基本思想均是將待校正電容與其所有的低位電容之和進(jìn)行比較,然后對(duì)二者之差進(jìn)行補(bǔ)償。針對(duì)非二進(jìn)制SAR ADC,本文提出了一種基于電容互換的數(shù)字域后臺(tái)校正。DAC中的終端電容被視為參考電容,每個(gè)輸入信號(hào)被量化兩次,在第二次量化時(shí)待校正的單位電容與參考電容交換位置。根據(jù)兩次量化結(jié)果之差,利用LMS算法對(duì)待校正的單位電容的數(shù)字權(quán)重進(jìn)行更新。為了減少所需校正的電容的個(gè)數(shù),本文還提出了帶雙參考電容的校正算法。3.自校正帶隙基準(zhǔn)的設(shè)計(jì)與實(shí)現(xiàn):帶隙基準(zhǔn)為ADC提供了一個(gè)不隨溫度和電源電壓變化的參考電壓,但傳統(tǒng)帶隙基準(zhǔn)的初始精度不高。為此,本文提出了一種自校正的帶隙基準(zhǔn)電路。電路上電后,通過交換需要匹配的器件的相對(duì)位置,可以得到兩個(gè)大小不同的初始基準(zhǔn)電壓。然后通過自動(dòng)修調(diào),使電路最終輸出的基準(zhǔn)電壓等于兩個(gè)初始基準(zhǔn)電壓的平均值。該設(shè)計(jì)達(dá)到了和斬波技術(shù)相同的效果,但避免了時(shí)鐘信號(hào)的持續(xù)作用,消除了電壓的抖動(dòng),同時(shí)也避免了傳統(tǒng)修調(diào)技術(shù)中需要對(duì)各顆芯片單獨(dú)進(jìn)行人工修調(diào)的弊端,提高了系統(tǒng)的智能化程度。該電路在65 nm CMOS工藝上進(jìn)行了流片驗(yàn)證。測(cè)試結(jié)果顯示,電路工作正常,校正后基準(zhǔn)電壓的3σ誤差率從±12.6%減小到±1.0%,溫度系數(shù)為23.6 ppm/°C,PSRR達(dá)到62.8 dB。4.基于非二進(jìn)制量化算法的SAR ADC的設(shè)計(jì)與實(shí)現(xiàn):本文設(shè)計(jì)了一個(gè)12位5 MSPS的非二進(jìn)制SAR ADC。為了進(jìn)一步提高速度,本文采用了帶Self-Timed控制模式的異步時(shí)序,并采用了一種自適應(yīng)延遲電路,使得異步時(shí)序中各位的量化時(shí)間可以根據(jù)實(shí)際的采樣率進(jìn)行調(diào)整。DAC選用了基于共模電壓復(fù)位的結(jié)構(gòu),基于整數(shù)權(quán)重來進(jìn)行設(shè)計(jì),并采用了分段電容陣列來降低總電容和面積。用自舉開關(guān)對(duì)輸入信號(hào)進(jìn)行采樣以提高采樣線性度。比較器采用了兩級(jí)預(yù)放大加鎖存的結(jié)構(gòu)以降低噪聲。進(jìn)行校正的數(shù)字電路通過Verilog代碼綜合后自動(dòng)生成,并與模擬電路部分集成在一顆芯片上。該ADC在65 nm CMOS工藝上進(jìn)行了流片驗(yàn)證,核心電路面積為0.77 mm×0.65 mm。測(cè)試結(jié)果顯示,電路工作正常,校正后各項(xiàng)性能指標(biāo)均有明顯改善,DNL和INL分別為0.73 LSB和1.24 LSB,SNDR和SFDR分別達(dá)到67.7 dB和85.5 dB,ENOB為11.0位,功耗約為6.87 mW。
[Abstract]:As a bridge to connect the analog signals of the external world and the internal digital signals in the system, analog digital converter (ADC) is widely used in the fields of digital multimedia, communication, biological medical and sensing control. Its speed, precision and power consumption have a direct impact on the processing capability of the whole system. The analog circuit design faces great challenges. But the successive approximation analog to analog digital converter (SAR ADC) contains only one analog module, its overall structure is simple and the power consumption is small, so it is easy to realize under the small size process and the advantages of other ADC structures are prominent. However, because of its serial working mode, the speed of SAR ADC The lower application is limited. On the other hand, as the resolution of ADC increases, the matching precision of the DAC capacitance is increased and the capacitance value increases sharply. This makes the SAR ADC be restricted by the dual power and speed in high precision applications. It is suitable for non binary quantization DAC structure, non binary DAC speed optimization design scheme, capacitor mismatch correction technique, asynchronous sequential circuit design and self-tuning bandgap reference circuit design. The main research work and innovation are as follows: 1. research on SAR ADC system architecture using non binary quantization algorithm: first of all, The conversion speed of the traditional binary SAR ADC is theoretically analyzed. As the accuracy of each DAC is quantified, the establishment precision of DAC needs to reach 0.5 LSB, which leads to the longer time required for DAC to limit the sampling rate of the ADC as a whole. The fraction can be introduced in the quantization process, so that the same input signal can be quantized by two different non binary codes. Thus, the requirement for the accuracy of DAC is relaxed. Then, there is a matching difference in the actual design for the fractional weighting algorithm, and there is a truncation error in the coding conversion, and the piecewise capacitance matrix can not be used. A quantization algorithm based on integer weights is proposed. On this basis, two kinds of DAC structures for non binary quantization are proposed, that is, the DAC based on the common mode voltage reset and the capacitive DAC. are placed in the middle of the redundant range by the reference voltage produced by the DAC, and the accuracy of the establishment of DAC is expanded from 0.5 LSB to redundancy. In the end, a scheme to optimize the design of DAC capacitors is proposed in order to maximize the advantage of redundancy to improve the overall conversion rate of.2.SAR ADC capacitor mismatch. In order to use small capacitors to achieve high precision SAR ADC, it is necessary to correct the mismatch of capacitance. This paper presents three different kinds of corrections. Positive technology, including analog domain front end correction, analog domain background correction and digital domain background correction, two analog domain corrections are applicable to binary SAR ADC. The basic idea is to compare the sum of the uncorrected capacitance to the sum of all low level capacitors, and then compensate the difference of the two. For non binary SAR ADC, this paper proposes The terminal capacitance in a digital domain backstage correction.DAC based on capacitance interchangeability is considered as a reference capacitor, each input signal is quantized two times and the unit capacitance to be corrected at the second time of quantization is exchanged with the reference capacitance. According to the difference between the two quantization results, the LMS algorithm is used to deal with the digital weight of the corrected unit capacitance. In order to reduce the number of capacitors required to be corrected, this paper also proposes the design and implementation of a self-tuning bandgap reference.3. with a double reference capacitance correction algorithm. The band gap reference provides a reference voltage without changing the temperature and the power supply voltage for the ADC, but the original precision of the traditional band gap reference is not high. A corrected bandgap reference circuit. After the circuit is on the circuit, two initial reference voltages of different sizes can be obtained by exchanging the relative position of the matched device. Then the voltage of the final output of the circuit is equal to the average of the two initial reference voltages by automatic tuning. The design achieves the same effect as the chopper technique. However, it avoids the continuous function of the clock signal and eliminates the jitter of the voltage. At the same time, it avoids the defects of the traditional trimming technology which needs to repair each chip separately, and improves the intelligentized degree of the system. The circuit has carried out the flow sheet verification in the 65 nm CMOS process. The test results show that the circuit works well and the calibrated datum. The 3 Sigma error rate of voltage is reduced from 12.6% to 1%, temperature coefficient is 23.6 ppm/ C, and PSRR reaches 62.8 dB.4. based on the design and implementation of SAR ADC based on non binary quantization algorithm. In this paper, a non binary SAR ADC. of 12 bit 5 MSPS is designed to further improve the speed. This paper uses the asynchronous sequence with Self-Timed control mode, and takes the asynchronous sequence with the Self-Timed control mode. Using an adaptive delay circuit, the quantization time in asynchronous sequence can be adjusted according to the actual sampling rate..DAC is based on the common mode voltage reset structure, based on the integer weight weight, and the sectional capacitance array is used to reduce the total capacitance and area. The input signal is sampled by the bootstrap switch. In order to improve the sampling linearity. The comparator uses a two stage preamplifier and latched structure to reduce the noise. The digital circuit is automatically generated by the Verilog code, and is integrated with the analog circuit on a chip. The ADC performs a flow sheet verification on the 65 nm CMOS process, with a core circuit area of 0.77 mm * 0.65 mm. The test results show that the circuit works well and the performance indexes are improved obviously. DNL and INL are 0.73 LSB and 1.24 LSB respectively. SNDR and SFDR are 67.7 dB and 85.5 dB respectively, ENOB is 11, and power consumption is 6.87 mW..
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2016
【分類號(hào)】：TN792

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