ALICE ITS單片式有源像素傳感器的低噪聲前端電子學(xué)的研究與實現(xiàn)
發(fā)布時間：2018-07-28 14:14
【摘要】：在2019年LHC第二次停止運行期間,ALICE將對其內(nèi)部徑跡探測器ITS進行升級。在徑跡探測器中,降低噪聲不僅可有效提高能量測量精度,同時也能提高探測效率,因此低噪聲是ITS升級的重要指標(biāo)之一。單片式有源像素探測器將傳感器和讀出電子學(xué)集成于同一硅片上,具有小輸入電容、低物質(zhì)量、易安裝等優(yōu)勢,因此ALICE ITS升級將采用單片式有源像素探測器。在一定功耗和帶寬條件下,減小前端電子學(xué)輸入電容和反饋電容可有效降低噪聲,因此本文針對低噪聲前端電路提出了四種降噪方法：1)、新的源漏極跟隨器電路結(jié)構(gòu)；2)、用兩層走線金屬間寄生電容實現(xiàn)小容量反饋電容,并通過適當(dāng)增加距離和面積、改變電容結(jié)構(gòu)等方法減小各像素間反饋電容的離散；3)、利用蒙特卡羅仿真實現(xiàn)在小面積約束條件下,降低不同像素間晶體管不一致引起的電荷閡值離散,從而降低由不同像素間電荷閾值離散引入的噪聲；4)、通過增加共源共柵晶體管減小輸入管柵漏間電壓增益,從而減小不同像素間密勒等效電容的離散,進一步降低不同像素間電荷閾值的離散。本文具體研究內(nèi)容和創(chuàng)新點主要體現(xiàn)在如下幾個方面：1、提出了新的源漏極跟隨器電路結(jié)構(gòu),減小了放大器輸入電容,從而降低了噪聲。源極跟隨器較單級放大器而言,其輸入晶體管柵源間寄生電容對放大器輸入電容沒有貢獻從而有較大的電荷-電壓轉(zhuǎn)換增益,被廣泛應(yīng)用于單片式有源像素探測器電荷讀出,然而,傳統(tǒng)的兩管結(jié)構(gòu)源極跟隨器仍有輸入管柵漏間寄生電容對輸入電容的貢獻,為了消除輸入管柵漏間寄生電容對輸入電容的貢獻,從而降低噪聲,本文提出了新型的五管結(jié)構(gòu)源漏極跟隨器,實現(xiàn)了源極和漏極都跟隨柵極電勢,消除了輸入晶體管柵源間和柵漏間寄生電容對輸入電容的貢獻,進一步減小了輸入電容,且其電壓增益比傳統(tǒng)源極跟隨器更接近1,從而增大了電荷-電壓轉(zhuǎn)換增益,降低了噪聲。該新型源漏極跟隨器電路已集成在了單片式有源像素探測器芯片INVESTIGATOR里,電路測試結(jié)果符合預(yù)期,同時,該芯片還通過增大傳感器PN結(jié)反向偏置電壓等方法降低PN結(jié)電容,進一步降低噪聲。INVESTIGATOR已使用55Fe輻射源進行測試,測試結(jié)果表明：當(dāng)PN結(jié)的反向偏置電壓從0V增大到-6V時,PN結(jié)電容減小了49%,即從5.96 fF減小到3.04fF,等效輸入噪聲電荷減小了36%,即從80e-減小到51 e-；新型源漏極跟隨器電路輸入電容比傳統(tǒng)源極跟隨器電路減小了9%，即從3.04fF減小到2.76 fF,等效輸入噪聲電荷減小了25%,即從51e-減小到38e-。2、用兩層走線金屬間寄生電容實現(xiàn)了小容量反饋電容,并通過適當(dāng)增加距離和面積、改變電容結(jié)構(gòu)等方法減小各像素間反饋電容的離散,以提高電荷-電壓轉(zhuǎn)換增益,達(dá)到提升電路信噪比的目的。電荷靈敏前置放大器可以靠減小反饋電容來獲得高轉(zhuǎn)換增益,降低噪聲,因此本文用兩層走線金屬間寄生電容實現(xiàn)了小容量反饋電容,并通過兩種方法減小不同像素間反饋電容的離散：其一是用不相鄰的兩層金屬增大反饋電容的距離和面積,其二是通過改變電容結(jié)構(gòu)減小邊緣效應(yīng)對反饋電容容值的影響。這種反饋電容已應(yīng)用于單片式有源像素探測器芯片pA_LP前端電子學(xué)的設(shè)計,仿真結(jié)果表明：通過第二層走線金屬和第四層走線金屬實現(xiàn)了0.2fF的反饋電容,電荷靈敏前置放大器在峰值時間為300ns時,等效輸入噪聲電荷約為18e-,每個像素功耗僅為45 nW。3、利用蒙特卡羅仿真實現(xiàn)了在小面積約束條件下,降低由不同像素間晶體管不一致引起的電荷閾值的離散,從而降低由不同像素間電荷閾值離散引入的噪聲。這種方法已應(yīng)用于單片式有源像素探測器芯片ALPIDE前端電子學(xué)不同像素間電荷閾值離散性的優(yōu)化,ALPIDE前端電子學(xué)是一個開環(huán)電荷讀出電路,由放大器和電流比較器組成,最大版圖面積限制為220 μm2。通過蒙特卡羅仿真分析每個晶體管對不同像素間電荷閾值離散的貢獻,根據(jù)其貢獻大小,對晶體管尺寸進行優(yōu)化,降低了由不同像素間晶體管不一致引起的電荷閾值離散。仿真結(jié)果表明：優(yōu)化后的前端電子學(xué)由不同像素間晶體管不一致引起的電荷閾值離散減小了67%,即從6.10e-減小到1.99e-,同時,隨機噪聲也減小了9%,即從3.70e-減小到3.37e-。4、通過增加共源共柵晶體管減小輸入晶體管柵漏間電壓增益,從而減小不同像素間密勒等效電容值的離散,進一步降低電荷閾值離散。這種方法已應(yīng)用于ALPIDE前端電子學(xué)不同像素間電荷閾值離散性的優(yōu)化,在第二級電流比較器輸入管漏極增加一個共源共柵晶體管,減小了電流比較器輸入管的柵漏間電壓增益,從而降低了由第二級輸入管柵漏間寄生電容在不同像素間不一致引起的電荷閾值離散。仿真結(jié)果表明：優(yōu)化后的前端電子學(xué)由第二級輸入晶體管柵漏間寄生電容不一致引起的電荷閾值離散減小了73%,即從2.19 e-/0.1fF減小到0.59e-/0.1fF。優(yōu)化后的前端讀出電路已集成在ALPIDE探測器里,每個像素僅消耗40 nW模擬功耗,ALPIDE芯片最終會使用在ALICE ITS升級探測器中。
[Abstract]:During the second stop operation of LHC in 2019, ALICE will upgrade its internal track detector ITS. In the track detector, reducing noise can not only effectively improve the accuracy of energy measurement, but also improve the detection efficiency. Therefore, low noise is one of the important indicators of the ITS upgrade. Electronics is integrated on the same silicon chip, with small input capacitance, low quality, easy installation and so on. Therefore, ALICE ITS upgrade will use a single chip active pixel detector. Under certain power and bandwidth conditions, reducing the input capacitance and feedback capacitance of front end electronics can reduce the noise effectively. Therefore, this paper proposes a low noise front end circuit. Four noise reduction methods: 1), the new source drain pole follower circuit structure, 2), the small capacity feedback capacitance is realized with the parasitic capacitance between the two layers of wire, and the discrete capacitance of each pixel is reduced by means of increasing the distance and area and changing the capacitance structure. 3), the Monte Carlo simulation is used to realize the small area constraint conditions. To reduce the charge threshold discreteness caused by the inconsistency of transistor inconsistencies among different pixels, thus reducing the noise caused by the discretization of the charge threshold between different pixels; 4) reducing the voltage gain of the input gate leakage by increasing the common source gate transistor, thus reducing the discretization of the Miller equal effective capacitance between different pixels and further reducing the charge between different pixels. The content and innovation of this paper are mainly reflected in the following aspects: 1, a new circuit structure of source drain follower is proposed, which reduces the input capacitance of the amplifier and reduces the noise. Compared with the single amplifier, the source follower has no parasitic capacitance between the gate source of the input transistor and the input capacitance of the amplifier. The contribution thus has a larger charge voltage conversion gain, which is widely used in single chip active pixel detector charge readout. However, the traditional two tube structure source follower still has the contribution of the input gate leakage parasitic capacitance to the input capacitance, in order to eliminate the contribution of the input gate leakage capacitance to the input capacitance and thus reduce the noise. In this paper, a new type of five tube structure source drain follower is proposed. The source and drain are all followed by the grid potential. The contribution of the input transistor gate and the gate leakage parasitic capacitance to the input capacitance is eliminated, and the input capacitance is further reduced, and the voltage gain is closer to 1 than the traditional source follower, thus increasing the charge voltage. The new source drain follower circuit has been integrated in the monolithic active pixel detector chip INVESTIGATOR, and the circuit test results conform to the expectation. At the same time, the chip also reduces the PN junction capacity by increasing the reverse bias voltage of the sensor PN junction, and further reduces the noise.INVESTIGATOR using 55Fe. The test results show that when the reverse bias voltage of PN junction is increased from 0V to -6V, the PN junction capacitance is reduced by 49%, that is, from 5.96 fF to 3.04fF, and the equivalent input noise charge decreases by 36%, that is, from 80e- to 51 e-, and the circuit input capacitance of the new source drain follower circuit is reduced by 9% than that of the traditional source follower circuit. From 3.04fF to 2.76 fF, the equivalent input noise charge is reduced by 25%, which is reduced from 51e- to 38e-.2, and a small capacity feedback capacitance is realized with the parasitic capacitance between the two layers of the wire. The capacitance of each pixel is reduced by increasing the distance and area and the capacitance structure is changed to increase the charge voltage conversion gain. To improve the signal to noise ratio of the circuit, the charge sensitive preamplifier can gain high conversion gain and reduce the noise by reducing the feedback capacitance. Therefore, a small capacity feedback capacitance is realized by two layer walk Wire parasitic capacitance, and the discretization of the feedback capacitance between different pixels is reduced by two methods: one is the non adjacent two. The layer metal increases the distance and area of the feedback capacitance, and the second is to reduce the influence of the edge effect on the capacitance of the feedback capacitance by changing the capacitance structure. This feedback capacitance has been applied to the design of the front end electronics of the monolithic active pixel detector chip pA_LP. The simulation results show that the second layers of wire and fourth layers of wire are solid. The feedback capacitance of 0.2fF is presented. When the charge sensitive preamplifier is at the peak time of 300ns, the equivalent input noise charge is about 18e-, and the power consumption of each pixel is only 45 nW.3. By Monte Carlo simulation, the discrete charge threshold caused by the inconsistency of the transistors between different pixels is reduced by the Monte Carlo simulation. This method has been applied to the optimization of the discreteness of the charge threshold between different pixels in the front-end electronics of the monolithic active pixel detector chip ALPIDE. The ALPIDE front-end electronics is an open loop charge readout circuit, consisting of an amplifier and a current comparator, and the maximum layout area is limited to 220 The contribution of each transistor to the discretization of the charge threshold between different pixels is analyzed by Monte Carlo simulation. According to its contribution, the transistor size is optimized, which reduces the discretization of the charge threshold caused by the inconsistency of transistors between different pixels. The simulation results show that the optimized front-end electronics is composed of transistors with different pixels. The discretization of the charge threshold caused by inconsistency decreases by 67%, that is, from 6.10e- to 1.99e-, and at the same time, the random noise is reduced by 9%, which is reduced from 3.70e- to 3.37e-.4. By increasing the common source gate transistor, the voltage gain of the gate leakage between the input transistors is reduced, thus the discretization of the Miller equivalent capacitance between different pixels is reduced and the charge threshold is further reduced. This method has been applied to the optimization of the discreteness of the charge threshold between different pixels in the ALPIDE front-end electronics. A common source transistor is added to the drain pole of the second stage current comparator, which reduces the voltage gain between the gate leakage of the current comparator input tube, and thus reduces the parasitic capacitance of the second stage input gate leakage. The simulation results show that the charge threshold discretization of the optimized front-end electronics decreases by 73%, which is caused by the disagreement of the parasitic capacitance of the second level input transistor gate leakage, that is, the front end readout circuit from 2.19 e-/0.1fF to the 0.59e-/0.1fF. optimization has been integrated into the ALPIDE detector. Each pixel consumes only 40 nW of analog power dissipation, and the ALPIDE chip will eventually be used in the ALICE ITS upgrade detector.
【學(xué)位授予單位】：華中師范大學(xué)
【學(xué)位級別】：博士
【學(xué)位授予年份】：2016
【分類號】：TP212
本文編號：2150478
[Abstract]:During the second stop operation of LHC in 2019, ALICE will upgrade its internal track detector ITS. In the track detector, reducing noise can not only effectively improve the accuracy of energy measurement, but also improve the detection efficiency. Therefore, low noise is one of the important indicators of the ITS upgrade. Electronics is integrated on the same silicon chip, with small input capacitance, low quality, easy installation and so on. Therefore, ALICE ITS upgrade will use a single chip active pixel detector. Under certain power and bandwidth conditions, reducing the input capacitance and feedback capacitance of front end electronics can reduce the noise effectively. Therefore, this paper proposes a low noise front end circuit. Four noise reduction methods: 1), the new source drain pole follower circuit structure, 2), the small capacity feedback capacitance is realized with the parasitic capacitance between the two layers of wire, and the discrete capacitance of each pixel is reduced by means of increasing the distance and area and changing the capacitance structure. 3), the Monte Carlo simulation is used to realize the small area constraint conditions. To reduce the charge threshold discreteness caused by the inconsistency of transistor inconsistencies among different pixels, thus reducing the noise caused by the discretization of the charge threshold between different pixels; 4) reducing the voltage gain of the input gate leakage by increasing the common source gate transistor, thus reducing the discretization of the Miller equal effective capacitance between different pixels and further reducing the charge between different pixels. The content and innovation of this paper are mainly reflected in the following aspects: 1, a new circuit structure of source drain follower is proposed, which reduces the input capacitance of the amplifier and reduces the noise. Compared with the single amplifier, the source follower has no parasitic capacitance between the gate source of the input transistor and the input capacitance of the amplifier. The contribution thus has a larger charge voltage conversion gain, which is widely used in single chip active pixel detector charge readout. However, the traditional two tube structure source follower still has the contribution of the input gate leakage parasitic capacitance to the input capacitance, in order to eliminate the contribution of the input gate leakage capacitance to the input capacitance and thus reduce the noise. In this paper, a new type of five tube structure source drain follower is proposed. The source and drain are all followed by the grid potential. The contribution of the input transistor gate and the gate leakage parasitic capacitance to the input capacitance is eliminated, and the input capacitance is further reduced, and the voltage gain is closer to 1 than the traditional source follower, thus increasing the charge voltage. The new source drain follower circuit has been integrated in the monolithic active pixel detector chip INVESTIGATOR, and the circuit test results conform to the expectation. At the same time, the chip also reduces the PN junction capacity by increasing the reverse bias voltage of the sensor PN junction, and further reduces the noise.INVESTIGATOR using 55Fe. The test results show that when the reverse bias voltage of PN junction is increased from 0V to -6V, the PN junction capacitance is reduced by 49%, that is, from 5.96 fF to 3.04fF, and the equivalent input noise charge decreases by 36%, that is, from 80e- to 51 e-, and the circuit input capacitance of the new source drain follower circuit is reduced by 9% than that of the traditional source follower circuit. From 3.04fF to 2.76 fF, the equivalent input noise charge is reduced by 25%, which is reduced from 51e- to 38e-.2, and a small capacity feedback capacitance is realized with the parasitic capacitance between the two layers of the wire. The capacitance of each pixel is reduced by increasing the distance and area and the capacitance structure is changed to increase the charge voltage conversion gain. To improve the signal to noise ratio of the circuit, the charge sensitive preamplifier can gain high conversion gain and reduce the noise by reducing the feedback capacitance. Therefore, a small capacity feedback capacitance is realized by two layer walk Wire parasitic capacitance, and the discretization of the feedback capacitance between different pixels is reduced by two methods: one is the non adjacent two. The layer metal increases the distance and area of the feedback capacitance, and the second is to reduce the influence of the edge effect on the capacitance of the feedback capacitance by changing the capacitance structure. This feedback capacitance has been applied to the design of the front end electronics of the monolithic active pixel detector chip pA_LP. The simulation results show that the second layers of wire and fourth layers of wire are solid. The feedback capacitance of 0.2fF is presented. When the charge sensitive preamplifier is at the peak time of 300ns, the equivalent input noise charge is about 18e-, and the power consumption of each pixel is only 45 nW.3. By Monte Carlo simulation, the discrete charge threshold caused by the inconsistency of the transistors between different pixels is reduced by the Monte Carlo simulation. This method has been applied to the optimization of the discreteness of the charge threshold between different pixels in the front-end electronics of the monolithic active pixel detector chip ALPIDE. The ALPIDE front-end electronics is an open loop charge readout circuit, consisting of an amplifier and a current comparator, and the maximum layout area is limited to 220 The contribution of each transistor to the discretization of the charge threshold between different pixels is analyzed by Monte Carlo simulation. According to its contribution, the transistor size is optimized, which reduces the discretization of the charge threshold caused by the inconsistency of transistors between different pixels. The simulation results show that the optimized front-end electronics is composed of transistors with different pixels. The discretization of the charge threshold caused by inconsistency decreases by 67%, that is, from 6.10e- to 1.99e-, and at the same time, the random noise is reduced by 9%, which is reduced from 3.70e- to 3.37e-.4. By increasing the common source gate transistor, the voltage gain of the gate leakage between the input transistors is reduced, thus the discretization of the Miller equivalent capacitance between different pixels is reduced and the charge threshold is further reduced. This method has been applied to the optimization of the discreteness of the charge threshold between different pixels in the ALPIDE front-end electronics. A common source transistor is added to the drain pole of the second stage current comparator, which reduces the voltage gain between the gate leakage of the current comparator input tube, and thus reduces the parasitic capacitance of the second stage input gate leakage. The simulation results show that the charge threshold discretization of the optimized front-end electronics decreases by 73%, which is caused by the disagreement of the parasitic capacitance of the second level input transistor gate leakage, that is, the front end readout circuit from 2.19 e-/0.1fF to the 0.59e-/0.1fF. optimization has been integrated into the ALPIDE detector. Each pixel consumes only 40 nW of analog power dissipation, and the ALPIDE chip will eventually be used in the ALICE ITS upgrade detector.
【學(xué)位授予單位】：華中師范大學(xué)
【學(xué)位級別】：博士
【學(xué)位授予年份】：2016
【分類號】：TP212
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，本文編號：2150478
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