應(yīng)用于高速電路中的電荷泵鎖相環(huán)設(shè)計(jì)
發(fā)布時(shí)間：2018-12-17 17:12
【摘要】：鎖相環(huán)是高速串行接口電路和無(wú)線(xiàn)通信系統(tǒng)中時(shí)鐘發(fā)生器的核心模塊。隨著信息流量不斷增長(zhǎng),系統(tǒng)復(fù)雜度日益提高,系統(tǒng)對(duì)鎖相環(huán)的工作速率、面積、功耗以及抖動(dòng)性能的要求也越來(lái)越高。本論文設(shè)計(jì)了用于高速串行接口電路中的電荷泵鎖相環(huán)。首先對(duì)電荷泵鎖相環(huán)進(jìn)行了系統(tǒng)分析,包括系統(tǒng)的線(xiàn)性模型、噪聲模型以及穩(wěn)定性。借助于MATLAB系統(tǒng)仿真軟件,確定了系統(tǒng)的環(huán)路參數(shù)。對(duì)比實(shí)際設(shè)計(jì)的晶體管級(jí)電路仿真結(jié)果和MATLAB系統(tǒng)模型的仿真結(jié)果,發(fā)現(xiàn)結(jié)果基本一致。電路設(shè)計(jì)中,由于輸入?yún)⒖碱l率較低,鑒頻鑒相器采用了經(jīng)典的基于鎖存器的結(jié)構(gòu),通過(guò)調(diào)節(jié)反饋回路的延時(shí),滿(mǎn)足消除鑒相死區(qū)的情況下,盡可能地減小了盲區(qū),提高了鑒相精度；電荷泵采用帶運(yùn)算放大器箝位的單端結(jié)構(gòu),其中尾電流源采用高擺幅的共源共柵結(jié)構(gòu),在得到高輸出阻抗的同時(shí)保證了較高的輸出擺幅,開(kāi)關(guān)管采用互補(bǔ)開(kāi)關(guān)以抑制電荷注入效應(yīng)；環(huán)路濾波器使用2階無(wú)源濾波器；壓控振蕩器使用三級(jí)差分環(huán)形結(jié)構(gòu),并加入了正反饋交叉耦合對(duì),使輸出波形電平轉(zhuǎn)換速度更快、對(duì)稱(chēng)性更好,達(dá)到降低相位噪聲的效果；由于分頻比較高,分頻器使用脈沖吞咽結(jié)構(gòu),其中預(yù)分頻器采用基于TSPCD觸發(fā)器的結(jié)構(gòu)。論文完成了電路設(shè)計(jì)、前仿真、版圖設(shè)計(jì)及后仿真。本設(shè)計(jì)基于SMIC 0.13μm CMOS工藝,由后仿真結(jié)果看出,TT工藝角下,當(dāng)輸入?yún)⒖紩r(shí)鐘頻率為2MHz, VCO輸出信號(hào)頻率為800MHz時(shí),鎖相環(huán)總功耗為5.4mA×3.3V,鎖定時(shí)間小于40μs,VCO輸出相位噪聲為-102dBc/Hz@1MHz,系統(tǒng)環(huán)路輸出峰峰抖動(dòng)最大值24.9ps@800MHz,版圖核心面積為0.315mm×0.285mm。
[Abstract]:PLL is the core module of clock generator in high speed serial interface circuit and wireless communication system. With the increasing of the information flow and the increasing complexity of the system, the requirements of the system for the speed, area, power consumption and jitter performance of the PLL are becoming higher and higher. In this paper, a charge pump phase locked loop (CPPLL) is designed for high speed serial interface circuit. Firstly, the charge pump phase-locked loop is analyzed systematically, including the linear model, noise model and stability of the system. With the help of MATLAB system simulation software, the loop parameters of the system are determined. Compared with the simulation results of the transistor level circuit designed in practice and the MATLAB system model, it is found that the results are basically the same. In the design of the circuit, because of the low input reference frequency, the phase discriminator adopts the classical structure based on latch. By adjusting the delay of the feedback loop, the blind area is reduced as much as possible under the condition of eliminating the dead zone of phase detection. The precision of phase detection is improved. The charge pump uses a single-terminal structure clamped with an operational amplifier, in which the tail current source adopts a high swing common-gate structure, which can obtain a high output impedance and ensure a higher output swing. The switching tube adopts complementary switch to suppress charge injection effect. The loop filter uses a second-order passive filter, the voltage-controlled oscillator uses a three-stage differential ring structure, and a positive feedback cross-coupling pair is added, which makes the output waveform level conversion faster and the symmetry better, thus reducing the phase noise. Because of the high frequency division, the frequency divider uses pulse swallowing structure, in which the predivider adopts the structure based on TSPCD flip-flop. Circuit design, pre-simulation, layout design and post-simulation are completed in this paper. The design is based on SMIC 0.13 渭 m CMOS process. The post-simulation results show that when the input reference clock frequency is 2 MHz and the VCO output signal frequency is 800MHz, the total power consumption of the PLL is 5.4mA 脳 3.3 V, and the locking time is less than 40 渭 s, when the input reference clock frequency is 2 MHz and the VCO output signal frequency is 800MHz. The phase noise of VCO output is -102dBc / Hz @ 1MHz, and the maximum output peak jitter of system loop is 24.9ps @ 800MHz. The core area of VCO is 0.315mm 脳 0.285mm.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類(lèi)號(hào)】：TN402
本文編號(hào)：2384539
[Abstract]:PLL is the core module of clock generator in high speed serial interface circuit and wireless communication system. With the increasing of the information flow and the increasing complexity of the system, the requirements of the system for the speed, area, power consumption and jitter performance of the PLL are becoming higher and higher. In this paper, a charge pump phase locked loop (CPPLL) is designed for high speed serial interface circuit. Firstly, the charge pump phase-locked loop is analyzed systematically, including the linear model, noise model and stability of the system. With the help of MATLAB system simulation software, the loop parameters of the system are determined. Compared with the simulation results of the transistor level circuit designed in practice and the MATLAB system model, it is found that the results are basically the same. In the design of the circuit, because of the low input reference frequency, the phase discriminator adopts the classical structure based on latch. By adjusting the delay of the feedback loop, the blind area is reduced as much as possible under the condition of eliminating the dead zone of phase detection. The precision of phase detection is improved. The charge pump uses a single-terminal structure clamped with an operational amplifier, in which the tail current source adopts a high swing common-gate structure, which can obtain a high output impedance and ensure a higher output swing. The switching tube adopts complementary switch to suppress charge injection effect. The loop filter uses a second-order passive filter, the voltage-controlled oscillator uses a three-stage differential ring structure, and a positive feedback cross-coupling pair is added, which makes the output waveform level conversion faster and the symmetry better, thus reducing the phase noise. Because of the high frequency division, the frequency divider uses pulse swallowing structure, in which the predivider adopts the structure based on TSPCD flip-flop. Circuit design, pre-simulation, layout design and post-simulation are completed in this paper. The design is based on SMIC 0.13 渭 m CMOS process. The post-simulation results show that when the input reference clock frequency is 2 MHz and the VCO output signal frequency is 800MHz, the total power consumption of the PLL is 5.4mA 脳 3.3 V, and the locking time is less than 40 渭 s, when the input reference clock frequency is 2 MHz and the VCO output signal frequency is 800MHz. The phase noise of VCO output is -102dBc / Hz @ 1MHz, and the maximum output peak jitter of system loop is 24.9ps @ 800MHz. The core area of VCO is 0.315mm 脳 0.285mm.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類(lèi)號(hào)】：TN402
【參考文獻(xiàn)】
相關(guān)期刊論文 前1條
1 ;Jitter analysis and modeling of a 10 Gbit/s SerDes CDR and jitter attenuation PLL[J];The Journal of China Universities of Posts and Telecommunications;2011年06期
，本文編號(hào)：2384539
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