高速低功耗SAR ADC的關(guān)鍵技術(shù)研究與系統(tǒng)設(shè)計
發(fā)布時間：2019-05-16 07:47
【摘要】：隨著通信行業(yè)的發(fā)展,特別是在5G時代的來臨之際,原有的通信設(shè)備性能已經(jīng)不能滿足不斷增長的通信應(yīng)用需求。這就促使通信設(shè)備必須向著能夠提供更高的通信帶寬,更快的數(shù)據(jù)傳輸速率的方向發(fā)展。另一方面,伴隨著物聯(lián)網(wǎng)與移動設(shè)備(如手機)等應(yīng)用領(lǐng)域的發(fā)展,單一設(shè)備往往要同時具有傳感,計算,通信等等功能,對芯片的功能集成度要求很高。在這些應(yīng)用領(lǐng)域,集成電路不僅要滿足性能方面的要求,更要滿足功耗方面的要求。在CMOS工藝的快速發(fā)展的前提下,半導(dǎo)體特征尺寸正在逐步減小。在該過程中,數(shù)字集成電路與模擬集成電路相比,能夠更好地在集成度,功耗和速度等方面受益。這使得數(shù)字集成電路能夠更好地滿足實際應(yīng)用中在速度、功耗和集成度方面不斷增長的需求,這也使得在電路層面對于信號的處理逐步從模擬端向數(shù)字端轉(zhuǎn)移。模數(shù)轉(zhuǎn)換器就是這樣一種能將現(xiàn)實世界中的模擬信號轉(zhuǎn)換為可被數(shù)字系統(tǒng)識別的數(shù)字信號的電路系統(tǒng),其作為連接模擬世界與數(shù)字系統(tǒng)的橋梁,顯得非常重要。模數(shù)轉(zhuǎn)換器的性能往往會成為全部體系性能的瓶頸。本文主要通過對高速低功耗SAR ADC的結(jié)構(gòu)和設(shè)計方法的研究,分析得出了在高速低功耗SAR ADC的設(shè)計中存在的主要問題。并在對已經(jīng)存在的相關(guān)方面的技術(shù)進行深入剖析的基礎(chǔ)上,針對之前的設(shè)計存在的不足之處,提出了改進型的分段預(yù)量化-旁路電容陣列式DAC和bootstrap電路。隨后以這兩種技術(shù)為基礎(chǔ)使用40nm CMOS工藝設(shè)計了一種高速低功耗單通道SAR ADC并進行了流片驗證,對本設(shè)計和其應(yīng)用的相應(yīng)的技術(shù)進行了驗證。芯片測試結(jié)果顯示本論文設(shè)計的ADC在1.2V供電電壓,340MS/s采樣速率情況下,ADC的有效位數(shù)為9.09bit,SFDR為73.55dB。
[Abstract]:With the development of the communication industry, especially with the advent of the 5G era, the performance of the original communication equipment can no longer meet the growing demand for communication applications. This makes the communication equipment must be able to provide higher communication bandwidth and faster data transmission rate. On the other hand, with the development of the Internet of things and mobile devices (such as mobile phones) and other application fields, a single device often has the functions of sensing, computing, communication and so on, which requires high functional integration of the chip. In these application fields, integrated circuits should not only meet the performance requirements, but also meet the requirements of power consumption. With the rapid development of CMOS process, the characteristic size of semiconductors is gradually decreasing. In this process, digital integrated circuits can benefit better in integration, power consumption and speed compared with analog integrated circuits. This makes the digital integrated circuit better meet the increasing demand of speed, power consumption and integration in practical applications, which also makes the signal processing gradually transfer from analog to digital at the circuit level. Analog-to-digital converter (ADC) is such a circuit system which can convert analog signal in real world into digital signal which can be recognized by digital system. It is very important to act as a bridge between analog world and digital system. The performance of A / D converter often becomes the bottleneck of all system performance. In this paper, the structure and design method of high speed and low power SAR ADC are studied, and the main problems in the design of high speed and low power SAR ADC are analyzed. Based on the in-depth analysis of the existing related technologies, and in view of the shortcomings of the previous design, an improved piecewise pre-quantification-bypass capacitor array DAC and bootstrap circuits are proposed. Then, based on these two technologies, a high speed and low power consumption single channel SAR ADC is designed by using 40nm CMOS process, and the chip verification is carried out, and the corresponding technology of this design and its application is verified. The chip test results show that under the condition of 1.2V power supply voltage and 340MS/s sampling rate, the effective bit of ADC is 9.09bit, and the ADC is 73.55dB. in the case of 1.2V power supply voltage and 340MS/s sampling rate, the effective bit of ADC is 9.09 bit and the SFDR is 73.55 dB.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN792
本文編號：2478131
[Abstract]:With the development of the communication industry, especially with the advent of the 5G era, the performance of the original communication equipment can no longer meet the growing demand for communication applications. This makes the communication equipment must be able to provide higher communication bandwidth and faster data transmission rate. On the other hand, with the development of the Internet of things and mobile devices (such as mobile phones) and other application fields, a single device often has the functions of sensing, computing, communication and so on, which requires high functional integration of the chip. In these application fields, integrated circuits should not only meet the performance requirements, but also meet the requirements of power consumption. With the rapid development of CMOS process, the characteristic size of semiconductors is gradually decreasing. In this process, digital integrated circuits can benefit better in integration, power consumption and speed compared with analog integrated circuits. This makes the digital integrated circuit better meet the increasing demand of speed, power consumption and integration in practical applications, which also makes the signal processing gradually transfer from analog to digital at the circuit level. Analog-to-digital converter (ADC) is such a circuit system which can convert analog signal in real world into digital signal which can be recognized by digital system. It is very important to act as a bridge between analog world and digital system. The performance of A / D converter often becomes the bottleneck of all system performance. In this paper, the structure and design method of high speed and low power SAR ADC are studied, and the main problems in the design of high speed and low power SAR ADC are analyzed. Based on the in-depth analysis of the existing related technologies, and in view of the shortcomings of the previous design, an improved piecewise pre-quantification-bypass capacitor array DAC and bootstrap circuits are proposed. Then, based on these two technologies, a high speed and low power consumption single channel SAR ADC is designed by using 40nm CMOS process, and the chip verification is carried out, and the corresponding technology of this design and its application is verified. The chip test results show that under the condition of 1.2V power supply voltage and 340MS/s sampling rate, the effective bit of ADC is 9.09bit, and the ADC is 73.55dB. in the case of 1.2V power supply voltage and 340MS/s sampling rate, the effective bit of ADC is 9.09 bit and the SFDR is 73.55 dB.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN792
【參考文獻】
相關(guān)碩士學(xué)位論文 前1條
1 汪肖陽;高速低功耗SAR ADC的研究與設(shè)計[D];電子科技大學(xué);2015年
，本文編號：2478131
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