納米工藝下集成電路的容軟錯誤鎖存器設(shè)計
發(fā)布時間：2019-05-17 13:54
【摘要】：集成電路產(chǎn)業(yè)是信息技術(shù)產(chǎn)業(yè)的基礎(chǔ)和核心,也是國家關(guān)注的戰(zhàn)略性產(chǎn)業(yè)。隨著半導(dǎo)體技術(shù)的飛躍式進(jìn)步,集成電路的性能在不斷提高的同時,所面臨的可靠性問題也越來受到人們的關(guān)注。隨著半導(dǎo)體工藝的飛速發(fā)展,集成電路的特征尺寸已進(jìn)入納米時代,供電電壓和敏感節(jié)點能儲存的電荷也隨之減小,CMOS電路受到輻射影響更容易發(fā)生軟錯誤。本文針對納米工藝下集成電路的軟錯誤問題,在研究現(xiàn)有加固鎖存器設(shè)計的基礎(chǔ)上,提出有效的加固鎖存器設(shè)計方案,本文主要工作如下:本文提出了能夠容忍單粒子單節(jié)點翻轉(zhuǎn)的STSRL鎖存器。該鎖存器采用了1P-2N單元、輸入分離的鐘控反相器以及C單元,使得本鎖存器對單粒子翻轉(zhuǎn)能夠?qū)崿F(xiàn)自恢復(fù),并且可以用于時鐘門控電路。STSRL鎖存器通過采用高速通路設(shè)計用以減小延遲,采用鐘控設(shè)計用以降低功耗。該鎖存器不僅能夠容忍單粒子單節(jié)點翻轉(zhuǎn),還能夠自恢復(fù),具有良好的加固能力。同時相比于已有的加固鎖存器其開銷大幅降低。HSPICE仿真結(jié)果表明,相比于HLR-CG1、HLR-CG2、TMR、HiPeR-CG鎖存器,STSRL鎖存器的功耗平均下降了 44.40%,延遲平均下降了 81%,PDP平均下降了 94.20%,面積開銷平均減少了 1.80%。本文提出了能夠容忍單粒子雙節(jié)點翻轉(zhuǎn)的SEDNUTL鎖存器,該鎖存器采用了雙模冗余容錯技術(shù),它能夠同時容忍單粒子單節(jié)點翻轉(zhuǎn)和單粒子雙節(jié)點翻轉(zhuǎn)。與同類型能容忍 DNU 的 DOUNT、DeltaDICE、DNCS、HRDUNT、NTHLTCH 加固鎖存器設(shè)計相比,SEDNUTL鎖存器的延遲平均下降了 90.66%,功耗平均增加了 14.74%,PDP平均下降了 90.27%,面積平均減少了 16.22%;而且在供電電壓、工作溫度和閾值電壓波動時,該鎖存器的延遲對其變化不敏感。
[Abstract]:Integrated circuit industry is the foundation and core of information technology industry, and it is also the strategic industry concerned by the state. With the rapid progress of semiconductor technology, the performance of integrated circuits is improving, and the reliability problems faced by integrated circuits have attracted more and more attention. With the rapid development of semiconductor technology, the characteristic size of integrated circuits has entered the nanometer era, and the power supply voltage and the charge stored by sensitive nodes are also reduced. CMOS circuits are more prone to soft errors affected by radiation. In order to solve the soft error problem of integrated circuits in nanotechnology, based on the study of the existing reinforcement latch design, an effective reinforcement latch design scheme is proposed in this paper. The main work of this paper is as follows: in this paper, a STSRL latch which can tolerate single particle single node flip is proposed. The latch adopts a 1P-2N unit, an input separated clock-controlled inverter and a C unit, so that the latch can realize self-recovery for a single particle flip. STSRL latch is designed to reduce delay by using high speed path design and clock control design to reduce power consumption. The latch can not only tolerate single particle single node flip, but also self-recovery, and has good reinforcement ability. At the same time, compared with the existing strengthened latch, the cost of STSRL latch is greatly reduced. HSPice simulation results show that compared with HLR-CG1,HLR-CG2,TMR,HiPeR-CG latch, the power consumption of STSRL latch is reduced by 44.40% on average, and the delay is reduced by 81% on average. On average, PDP decreased by 94.20%, and area cost decreased by 1.80%. In this paper, a SEDNUTL latch is proposed, which can tolerate single particle double node flip. The latch adopts dual mode redundant fault tolerant technique, which can tolerate single particle single node flip and single particle double node flip at the same time. Compared with the same type of DOUNT,DeltaDICE,DNCS,HRDUNT,NTHLTCH reinforcement latch design which can tolerate DNU, the delay of SEDNUTL latch is reduced by 92.66%, the power consumption is increased by 14.74%, and the PDP is reduced by 9027%. The area decreased by 16.22% on average. Moreover, when the supply voltage, operating temperature and threshold voltage fluctuate, the delay of the latch is not sensitive to its change.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN402
本文編號：2479143
[Abstract]:Integrated circuit industry is the foundation and core of information technology industry, and it is also the strategic industry concerned by the state. With the rapid progress of semiconductor technology, the performance of integrated circuits is improving, and the reliability problems faced by integrated circuits have attracted more and more attention. With the rapid development of semiconductor technology, the characteristic size of integrated circuits has entered the nanometer era, and the power supply voltage and the charge stored by sensitive nodes are also reduced. CMOS circuits are more prone to soft errors affected by radiation. In order to solve the soft error problem of integrated circuits in nanotechnology, based on the study of the existing reinforcement latch design, an effective reinforcement latch design scheme is proposed in this paper. The main work of this paper is as follows: in this paper, a STSRL latch which can tolerate single particle single node flip is proposed. The latch adopts a 1P-2N unit, an input separated clock-controlled inverter and a C unit, so that the latch can realize self-recovery for a single particle flip. STSRL latch is designed to reduce delay by using high speed path design and clock control design to reduce power consumption. The latch can not only tolerate single particle single node flip, but also self-recovery, and has good reinforcement ability. At the same time, compared with the existing strengthened latch, the cost of STSRL latch is greatly reduced. HSPice simulation results show that compared with HLR-CG1,HLR-CG2,TMR,HiPeR-CG latch, the power consumption of STSRL latch is reduced by 44.40% on average, and the delay is reduced by 81% on average. On average, PDP decreased by 94.20%, and area cost decreased by 1.80%. In this paper, a SEDNUTL latch is proposed, which can tolerate single particle double node flip. The latch adopts dual mode redundant fault tolerant technique, which can tolerate single particle single node flip and single particle double node flip at the same time. Compared with the same type of DOUNT,DeltaDICE,DNCS,HRDUNT,NTHLTCH reinforcement latch design which can tolerate DNU, the delay of SEDNUTL latch is reduced by 92.66%, the power consumption is increased by 14.74%, and the PDP is reduced by 9027%. The area decreased by 16.22% on average. Moreover, when the supply voltage, operating temperature and threshold voltage fluctuate, the delay of the latch is not sensitive to its change.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN402
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