發(fā)布時(shí)間：2019-05-19 11:47

【摘要】：隨著5G通信時(shí)代的到來,通信系統(tǒng)對(duì)模數(shù)轉(zhuǎn)換器(ADC)提出了更高的性能要求。單位時(shí)間內(nèi)需處理數(shù)據(jù)量不斷增加的同時(shí)信號(hào)失真度的要求也較高,因此,隨著各類便捷式電子產(chǎn)品的飛速發(fā)展對(duì)ADC的速度和精度提出了高標(biāo)準(zhǔn)的同時(shí),ADC的功耗也需進(jìn)一步的降低。在各種框架結(jié)構(gòu)中,流水線型ADC(Pipeline ADC)在眾多條件下具有較好的折中,被目前各種電子器件采用[1-2]。本文針對(duì)Pipeline ADC的功耗方面做深入研究,并設(shè)計(jì)了應(yīng)用于14bit 80MHz采樣頻率Pipeline ADC的關(guān)鍵單元電路模塊。根據(jù)14 bit 80MHz的Pipeline ADC性能要求,轉(zhuǎn)化到各個(gè)單元電路模塊的技術(shù)指標(biāo),依據(jù)單獨(dú)模塊的技術(shù)指標(biāo)提出以下各模塊的設(shè)計(jì)技術(shù)。提出了一種帶有正反饋環(huán)路增益自舉技術(shù)的運(yùn)算跨導(dǎo)放大器(OTA),達(dá)到了很高的低頻增益,不同于以往的補(bǔ)償技術(shù),提出一種新型的無密勒電容的頻率補(bǔ)償技術(shù),在確保系統(tǒng)穩(wěn)定工作的同時(shí)節(jié)省芯片面積。仿真表明:OTA的低頻增益為156d B,單位增益帶寬積為1.03GHz,輸出擺幅為2.5V,建立時(shí)間9.3ns,可滿足Pipeline ADC的性能要求。為降低Pipeline ADC的每級(jí)功耗,提出了一種新結(jié)構(gòu)的sub-ADC電路,動(dòng)態(tài)鎖存比較器采用由前置放大器和鎖存器構(gòu)成的架構(gòu),實(shí)現(xiàn)相鄰兩比較器共用一個(gè)前置放大器,并增加復(fù)位開關(guān)來降低“回踢”噪聲和消除兩鎖存器之間的干擾。仿真表明,sub-ADC功耗為改進(jìn)前的1/3,性能上可達(dá)到Pipeline ADC的指標(biāo)要求。對(duì)于偏置模塊帶隙基準(zhǔn)電路,提出一種新的高階溫度補(bǔ)償方法,通過共源-共柵電流鏡將負(fù)溫度系數(shù)電流降階,達(dá)到較低溫漂系數(shù)的電流�；�于對(duì)Pipeline ADC單元電路的設(shè)計(jì),采用SMIC 0.18μm標(biāo)準(zhǔn)CMOS 3.3V工藝,進(jìn)行電路晶體管級(jí)的設(shè)計(jì)。最后,利用Cadence軟件里virtuoso對(duì)運(yùn)算跨導(dǎo)放大器、動(dòng)態(tài)鎖存比較器以及帶隙基準(zhǔn)電路進(jìn)行了版圖設(shè)計(jì)。對(duì)版圖進(jìn)行DRC和LVS檢查,保證版圖設(shè)計(jì)的準(zhǔn)確性。
[Abstract]:With the advent of 5G communication era, communication system puts forward higher performance requirements for analog-to-digital converter (ADC). With the increasing amount of data per unit time, the requirement of signal distortion is also high. Therefore, with the rapid development of all kinds of convenient electronic products, the speed and accuracy of ADC have been put forward a high standard. The power consumption of ADC also needs to be further reduced. Among all kinds of frame structures, streamline ADC (Pipeline ADC) has a good compromise under many conditions, which is adopted by various electronic devices [1 鈮，

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