發(fā)布時(shí)間：2018-03-22 04:31

  本文選題：無(wú)線通信　切入點(diǎn)：CMOS功率放大器　出處：《中國(guó)科學(xué)技術(shù)大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著無(wú)線通信市場(chǎng)的持續(xù)繁榮與發(fā)展,小尺寸、低成本、低功耗和更加穩(wěn)定的無(wú)線通信設(shè)備越來(lái)越受到消費(fèi)者的青睞。CMOS工藝憑借其低成本以及易集成等優(yōu)勢(shì),已經(jīng)使得大部分的無(wú)線收發(fā)模塊都能在不犧牲性能的前提下采用CMOS工藝實(shí)現(xiàn)。然而功率放大器,作為無(wú)線收發(fā)機(jī)中耗能最多、尺寸最大的模塊,仍然是尚未被成功集成的幾個(gè)模塊之一。本文基于不同的無(wú)線通信應(yīng)用背景,對(duì)CMOS功放的相位和功率控制、可靠性、集成度和功率回退時(shí)的效率等幾個(gè)方面進(jìn)行了研究。針對(duì)超高頻RFID中自干擾信號(hào)的問(wèn)題,本文設(shè)計(jì)了一種相位和幅度可以數(shù)字控制的全集成功放。該功放由有源移相電路、緩沖電路和增益可控的功率放大電路組成。文中分析了各個(gè)模塊的基本原理和電路結(jié)構(gòu)。為了降低數(shù)控功放的AM-PM失真,增益可控的功率放大電路采用了一種電容補(bǔ)償技術(shù)。該功放采用130nm CMOS工藝實(shí)現(xiàn),仿真結(jié)果表明,數(shù)控功放在840MHz～960MHz的工作頻段內(nèi),相位均方根誤差小于0.21°,輸出功率變化小于1dBm,取得了較好的相位和幅度控制精度。將該功放應(yīng)用到自干擾抵消系統(tǒng),仿真結(jié)果顯示,功率為8dBm的自干擾信號(hào)最大可被抑制38dB。為了滿足超高頻RFID發(fā)射信號(hào)的要求,本文設(shè)計(jì)了一種全集成的線性功放。該功放采用一種帶有校準(zhǔn)電路的有源巴倫作為驅(qū)動(dòng)級(jí),同時(shí)該巴倫又提供了輸入信號(hào)單端轉(zhuǎn)差分的功能,節(jié)約了芯片面積。為了實(shí)現(xiàn)功放的全集成,本文還設(shè)計(jì)了一種可以實(shí)現(xiàn)差分轉(zhuǎn)單端功能的片上變壓器作為輸出匹配網(wǎng)絡(luò)。該功放在130 nmCMOS工藝下實(shí)現(xiàn),核心面積僅為0.83 mm-_2,仿真結(jié)果表明,功放在輸出功率為27dBm時(shí),效率能達(dá)到41%。為了支持更高的通信速率,現(xiàn)代無(wú)線通信信號(hào)的調(diào)制峰均比越來(lái)越高,功放將不可避免地要工作在功率回退狀態(tài)。為了提高功放在功率回退時(shí)的效率,本文在傳統(tǒng)負(fù)載調(diào)制技術(shù)的基礎(chǔ)上,設(shè)計(jì)了一種可動(dòng)態(tài)切換的雙模功放。文中分析了MOS開(kāi)關(guān)在關(guān)斷時(shí)功率損耗的來(lái)源,并在可調(diào)匹配網(wǎng)絡(luò)中采用了一種耐高壓的開(kāi)關(guān)電容來(lái)減少高輸出功率時(shí)的功率泄露。通過(guò)采用一種功率檢測(cè)控制電路對(duì)功放的偏置、晶體管尺寸和最優(yōu)負(fù)載進(jìn)行動(dòng)態(tài)調(diào)節(jié),功放在功率回退7dB時(shí)的效率可提升11.7%。在帶寬為40MHz的802.11n OFDM 64-QAM調(diào)制信號(hào)激勵(lì)下,功放在輸出功率為18dBm時(shí)的EVM和ACPR完全符合協(xié)議的線性度要求。
[Abstract]:With the continued prosperity and development of wireless communication market, wireless communication devices with small size, low cost, low power consumption and more stability are becoming more and more popular among consumers with the advantages of low cost and easy integration. It has enabled most wireless transceiver modules to be implemented using CMOS technology without sacrificing performance. However, power amplifiers are the most energy-consuming and largest modules in wireless transceivers. It is still one of the several modules that have not been successfully integrated. Based on the different wireless communication application background, the phase and power control and reliability of CMOS power amplifier are discussed in this paper. The integration level and the efficiency of power back time are studied in this paper. Aiming at the problem of self-interference signal in UHF RFID, a digitally controlled full-set amplifier is designed, which is composed of an active phase-shifting circuit. The basic principle and circuit structure of each module are analyzed in this paper. In order to reduce the AM-PM distortion of numerical control power amplifier, the circuit is composed of buffer circuit and gain controllable power amplifier circuit. A capacitive compensation technique is used in the gain controllable power amplifier, which is realized by 130nm CMOS technology. The simulation results show that the power amplifier is in the working frequency band of 840MHz~960MHz. The phase root mean square error is less than 0.21 擄and the output power is less than 1dBm.The phase and amplitude control accuracy is better. The simulation results show that the power amplifier is applied to the self-interference cancellation system. In order to satisfy the requirement of UHF RFID transmission signal, a fully integrated linear power amplifier is designed. The amplifier adopts an active Barron with calibrated circuit as the driving stage, and the self-interference signal with the power of 8dBm can be suppressed at a maximum of 38dB.In order to meet the requirements of the UHF RFID transmission signal, a fully integrated linear power amplifier is designed. At the same time, the Barron also provides the function of single-terminal differential input signal, which saves the chip area, in order to realize the full integration of power amplifier, This paper also designs a kind of on-chip transformer which can realize the function of differential switching single terminal as the output matching network. The power amplifier is realized in 130#en0# process, and the core area is only 0.83 mm-2. The simulation results show that the power amplifier can be used when the output power is 27dBm. Efficiency can reach 41. In order to support higher communication rate, the modulation peak to average ratio of modern wireless communication signal is higher and higher, the power amplifier will inevitably work in the state of power back, in order to improve the efficiency of power amplifier when power back, Based on the traditional load modulation technology, a dynamic switching dual-mode power amplifier is designed in this paper. The source of power loss when the MOS switch is turned off is analyzed. In the adjustable matching network, a high voltage tolerant switch capacitor is used to reduce the power leakage when the output power is high. The bias, transistor size and optimal load of the power amplifier are dynamically adjusted by a power detection control circuit. The efficiency of power amplifier can be improved by 11.7when the power is back 7dB. Under the excitation of 802.11n OFDM 64-QAM modulation signal with bandwidth 40MHz, the EVM and ACPR when the output power is 18dBm fully meet the linearity requirement of the protocol.
【學(xué)位授予單位】：中國(guó)科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN722.75

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本文編號(hào)：1647088