發(fā)布時(shí)間：2018-12-23 19:54

【摘要】：隨著集成電路的蓬勃發(fā)展,市場(chǎng)對(duì)低功耗器件需求日趨嚴(yán)重,業(yè)界對(duì)其中最具發(fā)展前景的隧穿場(chǎng)效應(yīng)晶體管(Tunnel Field-Effect Transistor,TFET)的研究也在不斷深入。國(guó)內(nèi)外最新研究表明,TFET工藝制作周期短、工作電壓低,通過量子隧穿效應(yīng)產(chǎn)生電流,這與傳統(tǒng)MOSFET依賴載流子漂移擴(kuò)散形成電流的方式不同。這種獨(dú)特的器件結(jié)構(gòu)使TFET的靜態(tài)功耗非常小,預(yù)示著TFET在低功耗器件領(lǐng)域有很大的應(yīng)用市場(chǎng)。本文目標(biāo)是完成基于TFET器件模型的單元特性仿真工作。論文在比較了TFET和傳統(tǒng)MOSFET的電學(xué)特性和導(dǎo)電機(jī)制之后,選取20 nm工藝下III-V族異質(zhì)結(jié)半導(dǎo)體化合物結(jié)構(gòu)的TFET器件模型,并對(duì)基于該TFET模型的標(biāo)準(zhǔn)單元進(jìn)行了參數(shù)仿真。仿真對(duì)象包括反相器、與非門、或與非門和動(dòng)態(tài)D觸發(fā)器等,仿真的參數(shù)包括傳播延時(shí)、輸出傳輸時(shí)間、短路能耗和靜態(tài)功耗。結(jié)果顯示,復(fù)雜邏輯門的單個(gè)輸入的傳播延時(shí)和一個(gè)TFET基本反相器延時(shí)相同,這與邏輯努力的理論相吻合。測(cè)量D觸發(fā)器時(shí)序參數(shù),結(jié)果表明該動(dòng)態(tài)D觸發(fā)器具有極小的建立、保持時(shí)間,電路性能較高。同時(shí)論文對(duì)基于該TFET器件模型的三種不同結(jié)構(gòu)的靜態(tài)存儲(chǔ)器進(jìn)行了仿真。仿真內(nèi)容包括讀噪聲容限和寫噪聲容限。第一和第二種TFET靜態(tài)存儲(chǔ)器的讀噪聲容限和寫噪聲容限效果不理想,第三種靜態(tài)存儲(chǔ)器在前兩種的基礎(chǔ)上進(jìn)行了結(jié)構(gòu)的調(diào)整,得到的讀噪聲容限128.1 m V,寫噪聲容限55.3 m V,較好的滿足了靜態(tài)存儲(chǔ)器讀穩(wěn)定性和寫穩(wěn)定性的要求。仿真結(jié)果在理論上證明了在靜態(tài)存儲(chǔ)器設(shè)計(jì)中TFET單元代替?zhèn)鹘y(tǒng)MOSFET單元的可行性。由于單元特性仿真的參數(shù)并未涉及到寄生參數(shù)信息,故本文可視為對(duì)TFET器件模型的基礎(chǔ)性研究,為后繼TFET器件代替?zhèn)鹘y(tǒng)MOSFET器件的技術(shù)研究方向提供一定的參考價(jià)值。
[Abstract]:With the rapid development of integrated circuits, the demand for low-power devices is becoming more and more serious, and the research on tunneling field effect transistors (Tunnel Field-Effect Transistor,TFET), which have the most promising prospect, is also getting deeper and deeper. The latest studies at home and abroad show that TFET process has short fabrication period and low working voltage, which is different from the traditional mode of MOSFET dependent carrier drift diffusion to generate current through quantum tunneling effect. This unique device structure makes the static power consumption of TFET very small, which indicates that TFET has a large application market in the field of low-power devices. The aim of this paper is to complete the simulation of cell characteristics based on TFET device model. After comparing the electrical properties and conductive mechanism between TFET and traditional MOSFET, the TFET device model of III-V heterojunction semiconductor compound structure under 20 nm process is selected, and the standard cell based on the TFET model is simulated. The simulation objects include inverter, non-gate, or non-gate and dynamic D flip-flop. The simulation parameters include propagation delay, output transmission time, short-circuit energy consumption and static power consumption. The results show that the propagation delay of a single input of the complex logic gate is the same as that of a TFET basic inverter, which is consistent with the theory of logic effort. The time series parameters of D flip-flop are measured. The results show that the dynamic D flip-flop has minimal establishment, holding time and high circuit performance. At the same time, three kinds of static memory based on the TFET device model are simulated. The simulation includes read noise tolerance and write noise tolerance. The read noise tolerance and write noise tolerance of the first and second TFET static memory are not ideal. The third static memory is adjusted on the basis of the first two, and the read noise tolerance is 128.1 MV. The write noise tolerance is 55.3 MV, which meets the requirements of the static memory read stability and write stability. The simulation results demonstrate the feasibility of replacing the traditional MOSFET cells with TFET cells in the static memory design. Because the parameters of cell characteristic simulation do not involve parasitic parameter information, this paper can be regarded as the basic research of TFET device model, which provides a certain reference value for the following TFET device to replace the traditional MOSFET device technology research direction.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN386

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